A transistor includes a gate, a channel layer, a gate insulation layer, a passivation layer, a liner, a first signal line, and a second signal line. The first signal line is embedded in the passivation layer to form a first via in the passivation layer and overlapping the channel layer. The second signal line is embedded in the passivation layer to form a second via in the passivation layer overlapping the channel layer. The second signal line is in contact with the channel layer. The liner includes an insulation region and a conductive region connected with the insulation region. The insulation region is disposed over the passivation layer and on sidewalls of the first via. The conductive region is disposed under a bottom of the first via and connected with the channel layer. The first signal line is electrically connected with the channel layer through the conductive region.

A transistor includes a gate, a channel layer, a gate insulation layer, a passivation layer, a liner, a first signal line, and a second signal line. The first signal line is embedded in the passivation layer to form a first via in the passivation layer and overlapping the channel layer. The second signal line is embedded in the passivation layer to form a second via in the passivation layer overlapping the channel layer. The second signal line is in contact with the channel layer. The liner includes an insulation region and a conductive region connected with the insulation region. The insulation region is disposed over the passivation layer and on sidewalls of the first via. The conductive region is disposed under a bottom of the first via and connected with the channel layer. The first signal line is electrically connected with the channel layer through the conductive region.

A semiconductor device includes first conductive lines provided on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, second conductive lines spaced apart from the first conductive lines in a second direction parallel to the top surface of the substrate, a gate electrode disposed between the first and second conductive lines and extended in the first direction, a plurality of channel patterns provided to enclose a side surface of the gate electrode and spaced apart from each other in the first direction, a ferroelectric pattern between each of the channel patterns and the gate electrode, and a gate insulating pattern between each of the channel patterns and the ferroelectric pattern. Each of the channel patterns is connected to a corresponding one of the first conductive lines and a corresponding one of the second conductive lines.

A method used in forming an electronic component comprising conductive material and ferroelectric material comprises forming a non-ferroelectric metal oxide-comprising insulator material over a substrate. A composite stack comprising at least two different composition non-ferroelectric metal oxides is formed over the substrate. The composite stack has an overall conductivity of at least 1×10.sup.2 Siemens/cm. The composite stack is used to render the non-ferroelectric metal oxide-comprising insulator material to be ferroelectric. Conductive material is formed over the composite stack and the insulator material. Ferroelectric capacitors and ferroelectric field effect transistors independent of method of manufacture are also disclosed.

A memory device includes first transistor over a semiconductor substrate, wherein the first transistor includes a first word line extending over the semiconductor substrate; a second transistor over the semiconductor substrate, wherein the second transistor includes a second word line extending over the first word line; a first air gap extending between the first word line and the second word line; a memory film extending along and contacting the first word line and the second word line; a channel layer extending along the memory film; a source line extending along the channel layer, wherein the memory film is between the source line and the word line; a bit line extending along the channel layer, wherein the memory film is between the bit line and the word line; and an isolation region between the source line and the bit line.

A memory device includes first transistor over a semiconductor substrate, wherein the first transistor includes a first word line extending over the semiconductor substrate; a second transistor over the semiconductor substrate, wherein the second transistor includes a second word line extending over the first word line; a first air gap extending between the first word line and the second word line; a memory film extending along and contacting the first word line and the second word line; a channel layer extending along the memory film; a source line extending along the channel layer, wherein the memory film is between the source line and the word line; a bit line extending along the channel layer, wherein the memory film is between the bit line and the word line; and an isolation region between the source line and the bit line.

Various aspects relate to a method of manufacturing a memory cell, the method including: forming a memory cell, wherein the memory cell comprises a spontaneously-polarizable memory element, wherein the spontaneously-polarizable memory element is in an as formed condition; and carrying out a preconditioning operation of the spontaneously-polarizable memory element to bring the spontaneously-polarizable memory element from the as formed condition into an operable condition to allow for a writing of the memory cell after the preconditioning operation is carried out.

A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a first layer stack and a second layer stack successively over a substrate, where the first layer stack and the second layer stack have a same layered structure that includes a layer of a first electrically conductive material over a layer of a first dielectric material, where the first layer stack extends beyond lateral extents of the second layer stack; forming a trench that extends through the first layer stack and the second layer stack; lining sidewalls and a bottom of the trench with a ferroelectric material; conformally forming a channel material in the trench over the ferroelectric material; filling the trench with a second dielectric material; forming a first opening and a second opening in the second dielectric material; and filling the first opening and the second opening with a second electrically conductive material.

A device includes a dielectric layer, a conductive layer, electrode layers and an oxide semiconductor layer. The dielectric layer has a first surface and a second surface opposite to the first surface. The conductive layer is disposed on the first surface of the dielectric layer. The electrode layers are disposed on the second surface of the dielectric layer. The oxide semiconductor layer is disposed in between the second surface of the dielectric layer and the electrode layers, wherein the oxide semiconductor layer comprises a material represented by formula 1 (In.sub.xSn.sub.yTi.sub.zM.sub.mO.sub.n). In formula 1, 0<x<1, 0≤y<1, 0<z<1, 0<m<1, 0<n<1, and M represents at least one metal.

A device includes a dielectric layer, a conductive layer, electrode layers and an oxide semiconductor layer. The dielectric layer has a first surface and a second surface opposite to the first surface. The conductive layer is disposed on the first surface of the dielectric layer. The electrode layers are disposed on the second surface of the dielectric layer. The oxide semiconductor layer is disposed in between the second surface of the dielectric layer and the electrode layers, wherein the oxide semiconductor layer comprises a material represented by formula 1 (In.sub.xSn.sub.yTi.sub.zM.sub.mO.sub.n). In formula 1, 0<x<1, 0≤y<1, 0<z<1, 0<m<1, 0<n<1, and M represents at least one metal.