A semiconductor memory structure and method of manufacturing a semiconductor memory structure are provided. The semiconductor memory structure comprises a cell array region, at least one connection region formed beside the cell array region and an interconnect structure formed on the connection region. The connection region comprises staircase portions and interval portions, which are alternately arranged and are separated by ferroelectric layers. The staircase portion comprises a staircase structure of alternating insulating layers and conductive layers, a dielectric layer formed on the staircase structure, and first conductive pillars formed over the staircase structure, extending into the dielectric layer and in contact with the staircase structure. The interval portion is formed beside the staircase portion and comprises second conductive pillars. The interconnect structure comprises vias formed on the first conductive pillars and the second conductive pillars in a XY staggered pattern.

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A sacrificial layer on a substrate, a P-type doped semiconductor layer having an N-well on the sacrificial layer, and a dielectric stack on the P-type doped semiconductor layer are subsequently formed. A channel structure extending vertically through the dielectric stack and the P-type doped semiconductor layer is formed. The dielectric stack is replaced with a memory stack, such that the channel structure extends vertically through the memory stack and the P-type doped semiconductor layer. The substrate and the sacrificial layer are removed to expose an end of the channel structure. Part of the channel structure abutting the P-type doped semiconductor layer is replaced with a semiconductor plug.

A 3-dimensional vertical memory string array includes high-speed ferroelectric field-effect transistor (FET) cells that are low-cost, low-power, or high-density and suitable for SCM applications. The memory circuits of the present invention provide random-access capabilities. The memory string may be formed above a planar surface of substrate and include a vertical gate electrode extending lengthwise along a vertical direction relative to the planar surface and may include (i) a ferroelectric layer over the gate electrode, (ii) a gate oxide layer; (iii) a channel layer provided over the gate oxide layer; and (iv) conductive semiconductor regions embedded in and isolated from each other by an oxide layer, wherein the gate electrode, the ferroelectric layer, the gate oxide layer, the channel layer and each adjacent pair of semiconductor regions from a storage transistor of the memory string, and wherein the adjacent pair of semiconductor regions serve as source and drain regions of the storage transistor.

Embodiments of a semiconductor memory device include a substrate having a first region with peripheral devices, a second region with one or more memory arrays, and a third region between the first and the second regions. The semiconductor memory device also includes a protective structure for peripheral devices. The protective structure for peripheral devices of the semiconductor memory device includes a first dielectric layer and a barrier layer disposed on the first dielectric layer. The protective structure for peripheral devices of the semiconductor memory device further includes a dielectric spacer formed on a sidewall of the barrier layer and a sidewall of the first dielectric layer, wherein the protective structure is disposed over the first region and at least a portion of the third region.

Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material contacting a first word line; an oxide semiconductor (OS) layer contacting a source line and a bit line, the FE material being disposed between the OS layer and the first word line; a dielectric material contacting the FE material, the FE material being between the dielectric material and the first word line; an inter-metal dielectric (IMD) over the first word line; a first contact extending through the IMD to the first word line, the first contact being electrically coupled to the first word line; a second contact extending through the dielectric material and the FE material; and a first conductive line electrically coupling the first contact to the second contact.

A semiconductor memory structure and method of manufacturing a semiconductor memory structure are provided. The semiconductor memory structure comprises a cell array region, at least one connection region formed beside the cell array region and an interconnect structure formed on the connection region. The connection region comprises staircase portions and interval portions, which are alternately arranged and are separated by ferroelectric layers. The staircase portion comprises a staircase structure of alternating insulating layers and conductive layers, a dielectric layer formed on the staircase structure, and first conductive pillars formed over the staircase structure, extending into the dielectric layer and in contact with the staircase structure. The interval portion is formed beside the staircase portion and comprises second conductive pillars. The interconnect structure comprises vias formed on the first conductive pillars and the second conductive pillars in a XY staggered pattern.

A semiconductor memory structure and method of manufacturing a semiconductor memory structure are provided. The semiconductor memory structure comprises alternatively arranged stacking portions and cell regions. Each cell region comprises two ferroelectric layers formed along the adjacent stacking portions; and at least one central portion disposed between the ferroelectric layers and comprises a first conductive structure and a second conductive structure separated by a channel isolation structure as well as two semiconductor layers formed along the ferroelectric layers. The first conductive structure comprises a contact portion and an extension portion. The contact portion is disposed between the semiconductor layers. The extension portion extends from the contact portion to the channel isolation structure and is separated from the semiconductor layers through dielectric layers.

A method for fabricating memory devices includes forming a first portion of a memory device that includes a first device portion and one or more first interface portions. The first device portion includes a plurality of first memory strings, each of which includes a plurality of first memory cells vertically separated from one another. Each of the one or more first interface portions, laterally abutted to one side of the first device portion, includes a plurality of first word lines (WLs). The method further includes forming a plurality of first source lines (SLs) and a plurality of first bit lines (BLs) in the first device portion. The method further includes forming a first seal ring structure that laterally encloses both the first device portion and the first interface portion concurrently with forming the pluralities of SLs and BLs.

A semiconductor die comprises: a device portion comprising an array of semiconductor devices extending in a first direction; and at least one interface portion located adjacent to an axial end of the device portion in the first direction. The at least one interface portion has a staircase profile in a vertical direction. The interface portion comprises: a stack comprising a plurality of gate layers and a plurality of insulating layers alternatively stacked on top of one another, and memory layers interposed between each of the plurality of gate layers and the plurality of insulating layers.

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory opening fill structures including a respective vertical semiconductor channel and a respective vertical stack of memory elements extending through the alternating stack in a memory array region, via contact structures contacting the stepped surfaces of the electrically conductive layers at each step in a staircase region, and a vertical stack of access transistors located between the staircase region and the memory array region.