A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.

Some embodiments include an integrated assembly having pillars arranged in an array. The pillars have channel regions between upper and lower source/drain regions. Gating structures are proximate to the channel regions and extend along a row direction. Digit lines are beneath the pillars, extend along a column direction, and are coupled with the lower source/drain regions. Linear structures are above the pillars and extend along the column direction. Bottom electrodes are coupled with the upper source/drain regions. The bottom electrodes have horizontal segments adjacent the upper source/drain regions and have vertical segments extending upwardly from the horizontal segments. The vertical segments are adjacent to lateral sides of the linear structures. Ferroelectric-insulative-material and top-electrode-material are over the bottom electrodes. A slit passes through the top-electrode-material, is directly over one of the linear structures, and extends along the column direction.

A semiconductor device includes a substrate, a fin protruding over the substrate, a gate structure over the fin, a bottom electrode over and electrically coupled to the gate structure, a ferroelectric layer around the bottom electrode, and a top electrode around the ferroelectric layer.

Some embodiments include an integrated assembly having first electrodes with top surfaces, and with sidewall surfaces extending downwardly from the top surfaces. The first electrodes are solid pillars. Insulative material is along the sidewall surfaces of the first electrodes. Second electrodes extend along the sidewall surfaces of the first electrodes and are spaced from the sidewall surfaces by the insulative material. Conductive-plate-material extends across the first and second electrodes, and couples the second electrodes to one another. Leaker-devices electrically couple the first electrodes to the conductive-plate-material and are configured to discharge at least a portion of excess charge from the first electrodes to the conductive-plate-material. Some embodiments include methods of forming integrated assemblies.

A semiconductor structure includes a first semiconductor die containing a recesses, and a second semiconductor die which is embedded in the recess in the first semiconductor die and is bonded to the first semiconductor die.

In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider.

Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The top electrode has interior surfaces defining a recess within an upper surface of the top electrode. A masking layer contacts a bottom of the recess and extends to over the upper surface of the top electrode. An interconnect extends through the masking layer and to the top electrode. The interconnect is directly over the upper surface of the top electrode.

Methods, systems, and devices for formation for memory cells are described. A semiconductor device (e.g., a memory die) may include asymmetrical rows of conductive pillars and one or more dielectric materials. For example, the memory die may include a set of conductive pillars that are arranged in rows that are asymmetrically spaced. Here, a first row of conductive pillars may be a first distance away from a second row of conductive pillars and a second, larger distance away from a third row of conductive pillars. Additionally, the memory die may include one or more dielectric materials. In some cases, when depositing a dielectric material as part of a self-aligning process, the material may conformally line exposed surfaces according to a substantially uniform depth, which may decrease a subsequent quantity of masking operations to form the memory die.

Methods, systems, and devices for formation for memory cells are described. A semiconductor device (e.g., a memory die) may include asymmetrical rows of conductive pillars and one or more dielectric materials. For example, the memory die may include a set of conductive pillars that are arranged in rows that are asymmetrically spaced. Here, a first row of conductive pillars may be a first distance away from a second row of conductive pillars and a second, larger distance away from a third row of conductive pillars. Additionally, the memory die may include one or more dielectric materials. In some cases, when depositing a dielectric material as part of a self-aligning process, the material may conformally line exposed surfaces according to a substantially uniform depth, which may decrease a subsequent quantity of masking operations to form the memory die.