Some embodiments include an assembly having first and second pillars. Each of the pillars has an inner edge and an outer edge. A first gate is proximate a channel region of the first pillar. A second gate is proximate a channel region of the second pillar. A shield line is between the first and second pillars. First and second bottom electrodes are over the first and second pillars, respectively; and are configured as first and second angle plates. An insulative material is over the first and second bottom electrodes. The insulative material may be ferroelectric or non-ferroelectric. A top electrode is over the insulative material. Some embodiments include methods of forming assemblies.

Some embodiments include an integrated assembly having first electrodes with top surfaces, and with sidewall surfaces extending downwardly from the top surfaces. The first electrodes are solid pillars. Insulative material is along the sidewall surfaces of the first electrodes. Second electrodes extend along the sidewall surfaces of the first electrodes and are spaced from the sidewall surfaces by the insulative material. Conductive-plate-material extends across the first and second electrodes, and couples the second electrodes to one another. Leaker-devices electrically couple the first electrodes to the conductive-plate-material and are configured to discharge at least a portion of excess charge from the first electrodes to the conductive-plate-material. Some embodiments include methods of forming integrated assemblies.

A semiconductor storage device and an electronic device that include a ferroelectric capacitor having a more optimized structure, as a memory cell are provided. A semiconductor storage device includes a field-effect transistor provided in an active region of a semiconductor substrate, a ferroelectric capacitor including a first capacitor electrode and a second capacitor electrode sandwiching a ferroelectric film, the first capacitor electrode being electrically connected to one of a source or a drain of the field-effect transistor, a source line electrically connected to the second capacitor electrode of the ferroelectric capacitor, and a bit line electrically connected to another one of the source or the drain of the field-effect transistor, in which a gate electrode of the field-effect transistor extends in a first direction across the active region, and the source line and the bit line extend in a second direction orthogonal to the first direction.

A semiconductor storage device and a multiplier-accumulator are provided that are capable of applying a sufficient voltage to a ferroelectric capacitor and are suitable for high integration. A semiconductor storage device includes: a transistor; and a ferroelectric capacitor that is formed by sandwiching a ferroelectric material between a pair of conductive materials, one of the pair of conductive materials being electrically connected to a gate electrode of the transistor, in which a channel of the transistor is three-dimensionally formed over a plurality of surfaces.

Integrated circuitry comprises a plurality of features horizontally arrayed in a two-dimensional (2D) lattice. The 2D lattice comprises a parallelogram unit cell having four lattice points and four straight-line sides between pairs of the four lattice points. The parallelogram unit cell has a straight-line diagonal there-across between two diagonally-opposed of the four lattice points. The straight-line diagonal is longer than each of the four straight-line sides. Individual of the features are at one of the four lattice points and occupy a maximum horizontal area that is horizontally elongated along a direction that is horizontally angled relative to each of the four straight-line sides. Other embodiments, including methods, are disclosed

A method of forming a memory device including forming a stack of silicon nitride layers and polysilicon layers that are alternating arranged, etching a serpentine trench in the stack of silicon nitride layers and polysilicon layers, forming a first isolation layer in the serpentine trench, removing one of the silicon nitride layers to form a recess between neighboring two of the polysilicon layers, and forming in sequence a doped polysilicon layer, a gate dielectric layer, and a conductive layer in the recess.

Embodiments of ferroelectric memory devices and methods for forming the ferroelectric memory devices are disclosed. In an example, a ferroelectric memory cell includes a first electrode, a second electrode, a doped ferroelectric layer disposed between the first electrode and the second electrode. The doped ferroelectric layer includes oxygen and one or more ferroelectric metals. The doped ferroelectric layer further includes a plurality of dopants including at least one dopant from one of Group II elements, Group III elements, or Lanthanide elements. The plurality of dopants are different from the one or more ferroelectric metals.

Various embodiments comprise apparatuses and methods of forming the apparatuses. In one embodiment, an exemplary apparatus includes a plurality of memory cells. At least a portion of the memory cells have a bottom electrode with each bottom electrode being at least partially electrically isolated from remaining ones of the bottom electrodes. At least one resistive interconnect electrically couples two or more of the bottom electrodes. The resistive interconnect is arranged to discharge at least a portion of excess charge from the two or more bottom electrodes. Additional apparatuses and methods of forming the apparatuses are disclosed.

In a method of manufacturing a semiconductor device according to an embodiment of the present disclosure, a stacked structure including interlayer insulating layers and interlayer sacrificial layers that are alternately stacked is formed on a substrate. A trench is formed passing through the stacked structure on the substrate. A crystalline liner insulating layer is formed on a sidewall of the trench. A ferroelectric insulating layer and a channel layer are formed on the crystalline liner insulating layer. The interlayer sacrificial layers and the crystalline liner insulating layer are selectively removed to form a recess selectively exposing the ferroelectric insulating layer. The recess is filled with a conductive layer to form an electrode layer.

Embodiments of ferroelectric memory devices and methods for forming the ferroelectric memory devices are disclosed. In an example, a ferroelectric memory cell includes a first electrode, a second electrode, a doped ferroelectric layer disposed between the first electrode and the second electrode. The doped ferroelectric layer includes oxygen and one or more ferroelectric metals. The doped ferroelectric layer further includes a plurality of dopants including at least one dopant from one of Group II elements, Group III elements, or Lanthanide elements. The plurality of dopants are different from the one or more ferroelectric metals.