A printed electronic device may comprise a plurality of contact pads arranged in a pattern, a plurality of electrode traces arranged in another pattern, the plurality of electrode traces comprising a set of bottom electrode traces and a set of top electrode traces, each electrode trace in electrical communication with an associated contact pad of the plurality of contact pads, and a plurality of memory cells, each memory cell located at an intersection of a pair of electrode traces of the plurality of electrode traces and comprising a bottom electrode layer formed from a region of one of the bottom electrode traces, a top electrode layer formed from a region of one of the top electrode traces, and a ferroelectric layer between the bottom and top electrode layers. The plurality of contact pads comprises at least one unmodified contact pad having a surface area, shape and size, the plurality of contact pads further comprising at least one modified contact pad having a reduced surface area, and a different size, a different shape, or both, as compared to the at least one unmodified contact pad.

Apparatuses and methods are disclosed that include ferroelectric memory and for accessing ferroelectric memory. An example method includes increasing a voltage of a first cell plate of a capacitor to change the voltage of a second cell plate of the capacitor, a second digit line, and a second sense node. The voltage of the second cell plate and the second digit line is decreased to change the voltage of the first cell plate, a first digit line, and a first sense node. The first node is driven to a first voltage and the second node is driven to a second voltage responsive to the voltage of the first node being greater than the second node. The first node is driven to the second voltage and the second node is driven to the first voltage responsive to the voltage of the first node being less than the second node.

Various embodiments of the present disclosure are directed towards a memory cell comprising a blocking layer configured to block diffusion of metal from an electrode of the memory cell to a ferroelectric layer of the memory cell. More particularly, the blocking layer and the ferroelectric layer are between a top electrode of the memory cell and a bottom electrode of the memory cell, which both comprise metal. Further, the blocking layer is between the ferroelectric layer and the electrode, which corresponds to one of the top and bottom electrodes. In some embodiments, the metal of the one of the top and bottom electrodes has a lowest electronegativity amongst the metals of top and bottom electrodes and is hence the most reactive and likely to diffuse amongst the metals of top and bottom electrodes.

Various embodiments of the present disclosure are directed towards a memory cell comprising a blocking layer configured to block diffusion of metal from an electrode of the memory cell to a ferroelectric layer of the memory cell. More particularly, the blocking layer and the ferroelectric layer are between a top electrode of the memory cell and a bottom electrode of the memory cell, which both comprise metal. Further, the blocking layer is between the ferroelectric layer and the electrode, which corresponds to one of the top and bottom electrodes. In some embodiments, the metal of the one of the top and bottom electrodes has a lowest electronegativity amongst the metals of top and bottom electrodes and is hence the most reactive and likely to diffuse amongst the metals of top and bottom electrodes.

An example of an apparatus includes a plurality of memory cells. At least a portion of the memory cells have a bottom electrode with each bottom electrode being at least partially electrically isolated from remaining ones of the bottom electrodes. At least one resistive interconnect electrically couples two or more of the bottom electrodes. The resistive interconnect is arranged to discharge at least a portion of excess charge from the two or more bottom electrodes. Additional apparatuses and methods of forming the apparatuses are disclosed.

An example of an apparatus includes a plurality of memory cells. At least a portion of the memory cells have a bottom electrode with each bottom electrode being at least partially electrically isolated from remaining ones of the bottom electrodes. At least one resistive interconnect electrically couples two or more of the bottom electrodes. The resistive interconnect is arranged to discharge at least a portion of excess charge from the two or more bottom electrodes. Additional apparatuses and methods of forming the apparatuses are disclosed.

A ferroelectric memory cell (FeRAM) is disclosed that includes an active device (e.g., a transistor) and a passive device (e.g., a ferroelectric capacitor) integrated in a substrate. The transistor and its gate contacts are formed on a front side of the substrate. A carrier wafer can be bonded to the active device to allow the active device to be inverted so that the passive device and associated contacts can be electrically coupled from a back side of the substrate.

A ferroelectric memory cell (FeRAM) is disclosed that includes an active device (e.g., a transistor) and a passive device (e.g., a ferroelectric capacitor) integrated in a substrate. The transistor and its gate contacts are formed on a front side of the substrate. A carrier wafer can be bonded to the active device to allow the active device to be inverted so that the passive device and associated contacts can be electrically coupled from a back side of the substrate.

Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.

Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.