Three-dimensional ferroelectric memory cell architectures are discussed related to improved memory cell performance and density. Such three-dimensional ferroelectric memory cell architectures include groups of vertically stacked transistors accessed by vertical bit lines and horizontal word lines. Groups of such stacks of transistors are arrayed laterally. Adjacent transistor stacks are separated by isolation material or memory structures inclusive of capacitor structures or plate line structures.

An example IC device includes a plurality of vertical transistors which may be part of memory cells, thus realizing vertical-transistor based memory. The IC device further includes a wordline, electrically continuous along a first longitudinal axis and electrically coupled to gates of a first subset of the transistors, and a control line that may be either a bitline or a plateline, electrically continuous along a second longitudinal axis and wrapping around at least portions of channel materials of a second subset of the transistors, where the first subset and the second subset have one transistor in common. At least one of the first longitudinal axis and the second longitudinal axis is not parallel to any edges or borders of the support structure, and, as a result, such a memory is referred to as “diagonal memory.” The transistors may be hysteretic transistors and/or may be further coupled to hysteretic capacitors.

An example IC device includes a plurality of vertical transistors which may be part of memory cells, thus realizing vertical-transistor based memory. The IC device further includes a wordline, electrically continuous along a first longitudinal axis and electrically coupled to gates of a first subset of the transistors, and a control line that may be either a bitline or a plateline, electrically continuous along a second longitudinal axis and wrapping around at least portions of channel materials of a second subset of the transistors, where the first subset and the second subset have one transistor in common. At least one of the first longitudinal axis and the second longitudinal axis is not parallel to any edges or borders of the support structure, and, as a result, such a memory is referred to as “diagonal memory.” The transistors may be hysteretic transistors and/or may be further coupled to hysteretic capacitors.

A semiconductor device and formation thereof. The semiconductor device including: a first bottom interconnect formed within a first dielectric layer and located within a logic area of the semiconductor device; a second bottom interconnect formed within the first dielectric layer and located within a memory area of the semiconductor device; and a memory device formed on top of the second bottom interconnect located within the memory area of the semiconductor device, wherein: a first metal material used to form the first bottom interconnect located in the logic area is different than a second metal material used to form the second bottom interconnect located in the memory area.

A memory cell arrangement is provided that may include: a plurality of electrode layers, wherein each of the plurality of electrode layers comprises a plurality of through holes, each of the plurality of through holes extending from a first surface to a second surface of a respective electrode layer; a plurality of electrode pillars, wherein each of the plurality of electrode pillars comprises a plurality of electrode portions, wherein each of the plurality of electrode portions is disposed within a corresponding one of the plurality of through holes; wherein the respective electrode layer and a respective electrode portion of the plurality of electrode portions form a first electrode and a second electrode of a capacitor and wherein at least one memory material portion is disposed in each of the plurality of through holes in a gap between the respective electrode layer and the respective electrode portion.

Three-dimensional hysteretic memory based on semiconductor nanoribbons is disclosed. An example memory cell may include a nanoribbon-based access transistor and a capacitor coupled to the access transistor, where the capacitor at least partially wraps around the nanoribbon in which the access transistor is formed. One or both of a gate stack of the access transistor and the capacitor insulator may include a hysteretic material/arrangement. Plurality of such memory cells may be provided in a single nanoribbon, and the nanoribbon may be one of a stack of nanoribbons provided above one another over a support structure. Incorporating hysteretic memory cells in different layers above a support structure by using stacks of semiconductor nanoribbons may allow significantly increasing density of hysteretic memory cells in a memory array having a given footprint area, or conversely, significantly reducing the footprint area of the memory array with a given density of hysteretic memory cells.

Three-dimensional hysteretic memory based on semiconductor nanoribbons is disclosed. An example memory cell may include a nanoribbon-based access transistor and a capacitor coupled to the access transistor, where the capacitor at least partially wraps around the nanoribbon in which the access transistor is formed. One or both of a gate stack of the access transistor and the capacitor insulator may include a hysteretic material/arrangement. Plurality of such memory cells may be provided in a single nanoribbon, and the nanoribbon may be one of a stack of nanoribbons provided above one another over a support structure. Incorporating hysteretic memory cells in different layers above a support structure by using stacks of semiconductor nanoribbons may allow significantly increasing density of hysteretic memory cells in a memory array having a given footprint area, or conversely, significantly reducing the footprint area of the memory array with a given density of hysteretic memory cells.

A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.

Some embodiments include an integrated assembly having a row of conductive posts. The conductive posts are spaced from one another by gaps. Leaker device material extends is within at least some of the gaps. An insulative material is along sidewalls of the conductive posts. A conductive structure is over the conductive posts. The conductive structure has downward projections extending into at least some of the gaps. The leaker device material is configured as segments along sides of the downward projections and extends from the sides to one or more of the conductive posts. Some embodiments include methods of forming integrated assemblies.

A method of forming an array of capacitors comprises forming a plurality of horizontally-spaced groups that individually comprise a plurality of horizontally-spaced lower capacitor electrodes having a capacitor insulator thereover. Adjacent of the groups are horizontally spaced farther apart than are adjacent of the lower capacitor electrodes within the groups. A void space is between the adjacent groups. An upper capacitor electrode material is formed in the void space and in the groups over the capacitor insulator and the lower capacitor electrodes. The upper capacitor electrode material in the void space connects the upper capacitor electrode material that is in the adjacent groups relative to one another. The upper capacitor electrode material less-than-fills the void space. At least a portion of the upper capacitor electrode material is removed from the void space to disconnect the upper capacitor electrode material in the adjacent groups from being connected relative to one another. A horizontally-elongated conductive line is formed atop and is directly electrically coupled to the upper capacitor electrode material in individual of the groups. Other methods, including structure independent of method of manufacture, are disclosed.