Provided is a semiconductor storage device and an electronic apparatus having a structure that is more suitable for miniaturization and high integration of memory cells. A semiconductor storage device includes: a recessed portion provided in a semiconductor substrate; a ferroelectric film provided along an inner side of the recessed portion; an electrode provided on the ferroelectric film so as to be embedded in the recessed portion; a first conductivity-type separation region provided in the semiconductor substrate under the recessed portion; and a second conductivity-type electrode region provided in the semiconductor substrate on at least one side of the recessed portion.

An example of an apparatus includes a plurality of memory cells. At least a portion of the memory cells have a bottom electrode with each bottom electrode being at least partially electrically isolated from remaining ones of the bottom electrodes. At least one resistive interconnect electrically couples two or more of the bottom electrodes. The resistive interconnect is arranged to discharge at least a portion of excess charge from the two or more bottom electrodes. Additional apparatuses and methods of forming the apparatuses are disclosed.

The present disclosure relates to a memory device, and more particularly, to a memory device including a substrate, a plurality of vertical structures disposed on the substrate and including insulation layers and lower electrodes, which are alternately laminated with each other, wherein the vertical structures are aligned in a first direction parallel to a top surface of the substrate and a second direction crossing the first direction, an upper electrode disposed on a top surface and side surfaces of each of the vertical structures, and a first dielectric layer disposed between the upper electrode and the vertical structures to cover the top surface and the side surfaces of each of the vertical structures. Here, the first dielectric layer includes a ferroelectric material.

A material having favorable ferroelectricity is provided. An embodiment of the present invention is a metal oxide film including a first layer and a second layer. The first layer contains first oxygen and hafnium, and the second layer contains second oxygen and zirconium. The hafnium and the zirconium are bonded to each other with the first oxygen positioned therebetween, and the second oxygen is bonded to the zirconium.

A material having favorable ferroelectricity is provided. An embodiment of the present invention is a metal oxide film including a first layer and a second layer. The first layer contains first oxygen and hafnium, and the second layer contains second oxygen and zirconium. The hafnium and the zirconium are bonded to each other with the first oxygen positioned therebetween, and the second oxygen is bonded to the zirconium.

Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.

A semiconductor storage device and an electronic device that include a ferroelectric capacitor having a more optimized structure, as a memory cell are provided. A semiconductor storage device includes a field-effect transistor provided in an active region of a semiconductor substrate, a ferroelectric capacitor including a first capacitor electrode and a second capacitor electrode sandwiching a ferroelectric film, the first capacitor electrode being electrically connected to one of a source or a drain of the field-effect transistor, a source line electrically connected to the second capacitor electrode of the ferroelectric capacitor, and a bit line electrically connected to another one of the source or the drain of the field-effect transistor, in which a gate electrode of the field-effect transistor extends in a first direction across the active region, and the source line and the bit line extend in a second direction orthogonal to the first direction.

A semiconductor storage device and an electronic device that include a ferroelectric capacitor having a more optimized structure, as a memory cell are provided. A semiconductor storage device includes a field-effect transistor provided in an active region of a semiconductor substrate, a ferroelectric capacitor including a first capacitor electrode and a second capacitor electrode sandwiching a ferroelectric film, the first capacitor electrode being electrically connected to one of a source or a drain of the field-effect transistor, a source line electrically connected to the second capacitor electrode of the ferroelectric capacitor, and a bit line electrically connected to another one of the source or the drain of the field-effect transistor, in which a gate electrode of the field-effect transistor extends in a first direction across the active region, and the source line and the bit line extend in a second direction orthogonal to the first direction.

A memory cell arrangement is provided that may include: one or more memory cells, each of the one or more memory cells including: an electrode pillar having a bottom surface and a top surface; a memory material portion surrounding a lateral surface portion of the electrode pillar; an electrode layer surrounding the memory material portion and the lateral surface portion of the electrode pillar, wherein the electrode pillar, the memory material portion, and the electrode layer form a capacitive memory structure; and a field-effect transistor structure comprising a gate structure, wherein the bottom surface of the electrode pillar faces the gate structure and is electrically conductively connected to the gate structure, and wherein the top surface of the electrode pillar faces away from the gate structure.

According to various aspects a memory cell is provided, the memory cell including: a first electrode; a second electrode; and a memory layer disposed between the first electrode and the second electrode, wherein the memory layer includes a first memory portion having a first concentration of oxygen vacancies and a second memory portion having a second concentration of oxygen vacancies different from the first concentration of oxygen vacancies.