A ferroelectric memory structure including a substrate, a ferroelectric capacitor structure, and a switch device is provided. The ferroelectric capacitor structure is disposed on the substrate. The ferroelectric capacitor structure includes at least one first electrode, first dielectric layers, a second electrode, and a ferroelectric material layer. The at least one first electrode and the first dielectric layers are alternately stacked. The second electrode penetrates through the first electrode. The ferroelectric material layer is disposed between the first electrode and the second electrode. The switch device is electrically connected to the ferroelectric capacitor structure.

A 3D device, the device including: a first level including logic circuits; a second level including a plurality of memory circuits, where the first level is bonded to the second level, where the bonded includes oxide to oxide bonds, and where the first level includes at least one voltage regulator circuit.

Systems, methods, and apparatuses are provided for self-aligned etch back for vertical three dimensional (3D) memory. One example method includes depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material to form a vertical stack, forming first vertical openings to form elongated vertical, pillar columns with first vertical sidewalls in the vertical stack, and forming second vertical openings through the vertical stack to expose second vertical sidewalls. Further, the example method includes removing portions of the semiconductor material to form first horizontal openings and depositing a fill in the first horizontal openings. The method can further include forming third vertical openings to expose third vertical sidewalls in the vertical stack and selectively removing the fill material to form a plurality of second horizontal openings in which to form horizontally oriented storage nodes.

A memory device comprising a three dimensional crosspoint memory array comprising a plurality of memory cells, wherein a memory cell is coupled between a first access line and a second access line and comprises an electrode coupled to a storage element, wherein the electrode comprises silicon carbide (Si.sub.xC.sub.y).

A memory device comprising a three dimensional crosspoint memory array comprising a plurality of memory cells, wherein a memory cell is coupled between a first access line and a second access line and comprises an electrode coupled to a storage element, wherein the electrode comprises silicon carbide (Si.sub.xC.sub.y).

Methods, systems, and devices for techniques to perform a sense operation are described. In some examples, a memory device may include a pair of transistor to precharge a digit line. A first transistor of the pair of transistors may be coupled with a first node and a second transistor of the pair of transistors may be coupled with a second node. In some cases, the first node and the second node may be selectively coupled via a transistor. The first and second transistors may be activated to precharge the first and second nodes. In some examples, a pulse may be applied to a capacitor coupled with the second node to transfer a charge to the digit line. In some cases, the cascode transistor may maintain or control the voltage of the digit line to be at or below an upper operating voltage of the memory cell.

Methods, systems, and devices for techniques to perform a sense operation are described. In some examples, a memory device may include a pair of transistor to precharge a digit line. A first transistor of the pair of transistors may be coupled with a first node and a second transistor of the pair of transistors may be coupled with a second node. In some cases, the first node and the second node may be selectively coupled via a transistor. The first and second transistors may be activated to precharge the first and second nodes. In some examples, a pulse may be applied to a capacitor coupled with the second node to transfer a charge to the digit line. In some cases, the cascode transistor may maintain or control the voltage of the digit line to be at or below an upper operating voltage of the memory cell.

Integrated circuits with embedded memory having multiple levels. Each memory array level includes ferroelectric capacitors coupled to an array of thin film access transistors according to a 1T-1F or 1T-many F bit-cell architecture. The levels of embedded memory are monolithically fabricated, one over the other, or after monolithically fabricating one level of embedded memory in a host IC structure, a second IC structure with another level of memory array is directly bonded to a front or backside of the host IC structure in a face-to-face or face-to-back orientation. The second IC structure may include additional peripheral CMOS circuitry, such as sense amps or decoders, or not.

A first type of ferroelectric capacitor comprises electrodes and an insulating layer comprising ferroelectric oxides. In some embodiments, the electrodes and the insulating layer comprise perovskite ferroelectric oxides. A second type of ferroelectric capacitor comprises a ferroelectric insulating layer comprising certain monochalcogenides. Both types of ferroelectric capacitors can have a coercive voltage that is less than one volt. Such capacitors are attractive for use in low-voltage non-volatile embedded memories for next-generation semiconductor manufacturing technologies.

A first type of ferroelectric capacitor comprises electrodes and an insulating layer comprising ferroelectric oxides. In some embodiments, the electrodes and the insulating layer comprise perovskite ferroelectric oxides. A second type of ferroelectric capacitor comprises a ferroelectric insulating layer comprising certain monochalcogenides. Both types of ferroelectric capacitors can have a coercive voltage that is less than one volt. Such capacitors are attractive for use in low-voltage non-volatile embedded memories for next-generation semiconductor manufacturing technologies.