An oxide semiconductor based FRAM is provided in the present invention, including a substrate, a write electrode on the substrate, a ferroelectric dielectric layer on the write electrode, an oxide semiconductor layer on the ferroelectric dielectric layer, a source and a drain respectively on the oxide semiconductor layer and spaced apart at a distance, wherein the source and the drain are further connected to a plate line and a bit line respectively, a gate insulating layer on the source, the drain and the oxide semiconductor layer, and a word line on the gate insulating layer, wherein the word line, the oxide semiconductor layer, the ferroelectric dielectric layer and the write electrode overlapping each other in a direction vertical to the substrate.

A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. Ferroelectric material is laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material. A parallel current leakage path is between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode. The parallel current leakage path is circuit-parallel the intrinsic current leakage path and of lower total resistance than the intrinsic current leakage path. Other aspects, including methods, are disclosed.

A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. Ferroelectric material is laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material. A parallel current leakage path is between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode. The parallel current leakage path is circuit-parallel the intrinsic current leakage path and of lower total resistance than the intrinsic current leakage path. Other aspects, including methods, are disclosed.

The present invention relates to an integrated electronic circuit and method of making comprising a first transistor (1) and a ferroelectric capacitor (2). The ferroelectric capacitor (2) comprises a first electrode layer composed of a non-ferroelectric material, a ferroelectric interlayer having a thickness that is less than the thickness of the first electrode layer, and a second electrode layer composed of a non-ferroelectric material, wherein the ferroelectric interlayer is arranged between the first electrode layer and the second electrode layer, and the first electrode layer is electrically conductively connected to a gate terminal of the first transistor (1).

Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.

A ferroelectric structure includes a first polarization enhancement film on a ferroelectric film, wherein the ferroelectric film has a first net polarization in a first direction oriented from the ferroelectric film toward the first polarization enhancement film. The first polarization enhancement film has a second net polarization in a second direction crossing the first direction.

Some embodiments include an integrated assembly having an array of vertically-extending active regions. Each of the active regions is contained within a four-sided area. Conductive gate material is configured as first conductive structures. Each of the first conductive structures extends along a row of the array. The first conductive structures include segments along three of the four sides of each of the four-sided areas. Second conductive structures are under the active regions and extend along columns of the array. Third conductive structures extend along the rows of the array and are adjacent the fourth sides of the four-sided areas. Storage-elements are coupled with the active regions. Some embodiments include methods of forming integrated assemblies.

A method used in forming an electronic component comprising conductive material and ferroelectric material comprises forming a non-ferroelectric metal oxide-comprising insulator material over a substrate. A composite stack comprising at least two different composition non-ferroelectric metal oxides is formed over the substrate. The composite stack has an overall conductivity of at least 1×10.sup.2 Siemens/cm. The composite stack is used to render the non-ferroelectric metal oxide-comprising insulator material to be ferroelectric. Conductive material is formed over the composite stack and the insulator material. Ferroelectric capacitors and ferroelectric field effect transistors independent of method of manufacture are also disclosed.

A method used in forming an electronic component comprising conductive material and ferroelectric material comprises forming a non-ferroelectric metal oxide-comprising insulator material over a substrate. A composite stack comprising at least two different composition non-ferroelectric metal oxides is formed over the substrate. The composite stack has an overall conductivity of at least 1×10.sup.2 Siemens/cm. The composite stack is used to render the non-ferroelectric metal oxide-comprising insulator material to be ferroelectric. Conductive material is formed over the composite stack and the insulator material. Ferroelectric capacitors and ferroelectric field effect transistors independent of method of manufacture are also disclosed.

The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer. The capacitor stack further comprises first and second barrier metal layers on respective ones of the first and second crystalline conductive oxide electrodes on opposing sides of the polar layer