The present invention relates to a semiconductor structure and a method for forming the same, and a memory and a method for forming the same. The method for forming the semiconductor structure includes: providing a substrate on which a sacrificial layer and an active layer located on the sacrificial layer are formed; patterning the active layer to form several discrete active pillars; removing the sacrificial layer to form a gap; forming a bit line within the gap; and forming a semiconductor pillar on the top of the active pillar. The above method can reduce the planar size of the transistor and increase the storage density of the memory.

A memory device includes metal interconnect structures embedded within dielectric material layers that overlie a top surface of a substrate, a thin film transistor embedded in a first dielectric material layer selected from the dielectric material layers, and is vertically spaced from the top surface of the substrate, and a ferroelectric memory cell embedded within the dielectric material layers. A first node of the ferroelectric memory cell is electrically connected to a node of the thin film transistor through a subset of the metal interconnect structures that is located above, and vertically spaced from, the top surface of the substrate.

A memory device includes metal interconnect structures embedded within dielectric material layers that overlie a top surface of a substrate, a thin film transistor embedded in a first dielectric material layer selected from the dielectric material layers, and is vertically spaced from the top surface of the substrate, and a ferroelectric memory cell embedded within the dielectric material layers. A first node of the ferroelectric memory cell is electrically connected to a node of the thin film transistor through a subset of the metal interconnect structures that is located above, and vertically spaced from, the top surface of the substrate.

An integrated chip includes a memory cell within a BEOL metal interconnect. The memory cell may be an FeRAM memory cell. The memory cell is formed over a plurality of openings in a dielectric structure that includes an inter-level dielectric layer. The openings may be form an array or another two-dimensional pattern. The layers of the memory cell line the openings whereby each of a lower electrode layer, a data storage layer, and an upper electrode descend into the openings. The lower electrode layer may pass through an etch stop layer and contact a lower interconnect. There may be a plurality of top electrode vias. The top electrode vias may be offset from the opening. This memory cell structure provides a large area, which leads to low threshold voltages.

An integrated chip includes a memory cell within a BEOL metal interconnect. The memory cell may be an FeRAM memory cell. The memory cell is formed over a plurality of openings in a dielectric structure that includes an inter-level dielectric layer. The openings may be form an array or another two-dimensional pattern. The layers of the memory cell line the openings whereby each of a lower electrode layer, a data storage layer, and an upper electrode descend into the openings. The lower electrode layer may pass through an etch stop layer and contact a lower interconnect. There may be a plurality of top electrode vias. The top electrode vias may be offset from the opening. This memory cell structure provides a large area, which leads to low threshold voltages.

A method for fabricating a semiconductor device includes the steps of forming a first inter-metal dielectric (IMD) layer on a substrate, forming a first trench and a second trench in the first IMD layer, forming a bottom electrode in the first trench and the second trench, forming a ferroelectric (FE) layer on the bottom electrode, and then forming a top electrode on the FE layer to form a ferroelectric random access memory (FeRAM).

A method for fabricating a semiconductor device includes the steps of forming a first inter-metal dielectric (IMD) layer on a substrate, forming a first trench and a second trench in the first IMD layer, forming a bottom electrode in the first trench and the second trench, forming a ferroelectric (FE) layer on the bottom electrode, and then forming a top electrode on the FE layer to form a ferroelectric random access memory (FeRAM).

The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer. The capacitor stack further comprises first and second barrier metal layers on respective ones of the first and second crystalline conductive oxide electrodes on opposing sides of the polar layer

The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer. The capacitor stack further comprises first and second barrier metal layers on respective ones of the first and second crystalline conductive oxide electrodes on opposing sides of the polar layer

A method for manufacturing a semiconductor device may include: forming a plurality of stacked structures over a substrate, the substrate including one or more peripheral circuit regions and one or more cell regions, the stacked structures including first conductive lines and initial memory cells respectively disposed over the first conductive lines, each of the stacked structures extending in a first direction; forming a first insulating layer between the stacked structures; forming second conductive lines over the stacked structures and the first insulating layer, each of the second conductive lines extending in a second direction; forming memory cells by etching the initial memory cells exposed by the second conductive lines; forming a second insulating layer between the second conductive lines and between the memory cells; and removing the first conductive lines, the memory cells, and the second conductive lines in the peripheral circuit regions.