A semiconductor device includes a substrate, a fin protruding over the substrate, a gate structure over the fin, a bottom electrode over and electrically coupled to the gate structure, a ferroelectric layer around the bottom electrode, and a top electrode around the ferroelectric layer.

Various embodiments of the present disclosure are directed towards a memory cell in which an interfacial layer is on a bottom of a ferroelectric layer, between a bottom electrode and a ferroelectric layer. The interfacial layer is a different material than the bottom electrode and the ferroelectric layer and has a top surface with high texture uniformity compared to a top surface of the bottom electrode. The interfacial layer may, for example, be a dielectric, metal oxide, or metal that is: (1) amorphous; (2) monocrystalline; (3) crystalline with low grain size variation; (4) crystalline with a high percentage of grains sharing a common orientation; (5) crystalline with a high percentage of grains having a small grain size; or 6) any combination of the foregoing. It has been appreciated that such materials lead to high texture uniformity at the top surface of the interfacial layer.

Some embodiments include an integrated assembly having first and second pillars of semiconductor material. The first pillar includes a first source/drain region, and the second pillar includes a second source/drain region. First and second bottom electrodes are coupled with the first and second source/drain regions, respectively. The first and second source/drain regions are spaced from one another by an intervening region. First and second leaker-device-structures extend into the intervening region from the first and second bottom electrodes, respectively. Top-electrode-material extends into the intervening region and contacts the first and second leaker-device-structures. Ferroelectric-insulative-material is between the top-electrode-material and the bottom electrodes. Some embodiments include methods of forming integrated assemblies.

There is provided a semiconductor storage device that is allowed to obtain a sufficient margin for operation. The semiconductor storage device includes: a field-effect transistor; an interlayer insulating film; a contact; a first wiring layer; a first insulating layer; an opening section; and a ferroelectric capacitor. The field-effect transistor is provided in a semiconductor substrate. The interlayer insulating film is provided on the semiconductor substrate. The contact penetrates the interlayer insulating film and is electrically coupled to a drain of the field-effect transistor. The first wiring layer is provided on the contact. The first insulating layer is provided on the interlayer insulating film and has the first wiring layer buried therein. The opening section is provided in the first insulating layer and the interlayer insulating film from a layer upper than the first wiring layer. The ferroelectric capacitor is provided in the opening section and electrically coupled to a source of the field-effect transistor.

There is provided a semiconductor storage device that is allowed to obtain a sufficient margin for operation. The semiconductor storage device includes: a field-effect transistor; an interlayer insulating film; a contact; a first wiring layer; a first insulating layer; an opening section; and a ferroelectric capacitor. The field-effect transistor is provided in a semiconductor substrate. The interlayer insulating film is provided on the semiconductor substrate. The contact penetrates the interlayer insulating film and is electrically coupled to a drain of the field-effect transistor. The first wiring layer is provided on the contact. The first insulating layer is provided on the interlayer insulating film and has the first wiring layer buried therein. The opening section is provided in the first insulating layer and the interlayer insulating film from a layer upper than the first wiring layer. The ferroelectric capacitor is provided in the opening section and electrically coupled to a source of the field-effect transistor.

A semiconductor storage device includes a field-effect transistor, an interlayer insulation film, a source contact, an opening, and a capacitor. The field-effect transistor is provided on a semiconductor substrate. The interlayer insulation film is provided on the semiconductor substrate. The source contact runs through the interlayer insulation film and is electrically coupled to a source of the field-effect transistor. The opening is provided in a region of the interlayer insulation film including the source contact and allows the source contact to project therein. The capacitor includes a lower electrode, a ferroelectric film, and an upper electrode. The lower electrode is provided along an inside shape of the opening. The ferroelectric film is provided on the lower electrode. The upper electrode is provided on the ferroelectric film to fill the opening.

A transistor includes a first gate electrode, a composite channel layer, a first gate dielectric layer, and source/drain contacts. The composite channel layer is over the first gate electrode and includes a first capping layer, a crystalline semiconductor oxide layer, and a second capping layer stacked in sequential order. The first gate dielectric layer is located between the first gate electrode and the composite channel layer. The source/drain contacts are disposed on the composite channel layer.

Various aspects relate to a memory cell including a field-effect transistor structure and a capacitive memory structure, wherein the capacitive memory structure includes at least one spontaneously polarizable memory element, and wherein the field-effect transistor structure includes a source region, a drain region, a channel region extending between the source region and the drain region, and a gate structure disposed at the channel region, wherein the gate structure of the field-effect transistor structure substantially overlaps the source region of the field-effect transistor structure and/or the drain region of the field-effect transistor structure.

Various aspects relate to a memory cell including a field-effect transistor structure and a capacitive memory structure, wherein the capacitive memory structure includes at least one spontaneously polarizable memory element, and wherein the field-effect transistor structure includes a source region, a drain region, a channel region extending between the source region and the drain region, and a gate structure disposed at the channel region, wherein the gate structure of the field-effect transistor structure substantially overlaps the source region of the field-effect transistor structure and/or the drain region of the field-effect transistor structure.

The invention provides a non-volatile storage element and non-volatile storage device employing a ferroelectric material with low power consumption, excellent high reliability, and especially write/erase endurance, which can be mixed with advanced CMOS logic. The non-volatile storage element has at least a first conductive layer, a second conductive layer, and a ferroelectric layer composed of a metal oxide between both conductive layers, with a buffer layer having oxygen ion conductivity situated between the ferroelectric layer and the first conductive layer and/or second conductive layer. An interface layer composed of a single-layer film or a multilayer film may be also provided between the first conductive layer and the ferroelectric layer, the interface layer as a whole having higher dielectric constant than silicon oxide, and when the buffer layer is present between the first conductive layer and the ferroelectric layer, the interface layer is situated between the first conductive layer and the buffer layer. The non-volatile storage device comprises at least a memory cell array comprising low-power-consumption ferroelectric memory elements formed in a two-dimensional or three-dimensional configuration, and a control circuit. The ferroelectric layer is scalable to 10 nm or smaller and is fabricated at a low temperature of ≤400° C., and is subjected to low temperature thermal annealing treatment at ≤400° C. after the buffer layer has been formed, to provide high reliability.