In the examples disclosed herein, a memory array can have a first group of memory cells coupled to a first digit line at a first level and a second group of memory cells coupled to a second digit line at the first level. A third digit line can be at a second level and can be coupled to a main sense amplifier. A first vertical thin film transistor (TFT) can be at a third level between the first and second levels can be coupled between the first digit line and the third digit line. A second vertical TFT can be at the third level and can be coupled between the second digit line and the third digit line. A local sense amplifier can be coupled to the first and second digit lines.

Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.

Some embodiments include an integrated assembly having a conductive structure, an annular structure extending through the conductive structure, and an active-material-structure lining an interior periphery of the annular structure. The annular structure includes dielectric material. The active-material-structure includes two-dimensional-material. Some embodiments include methods of forming integrated assemblies.

A memory cell arrangement is provided that may include: one or more memory cells, each of the one or more memory cells including: an electrode pillar having a bottom surface and a top surface; a memory material portion surrounding a lateral surface portion of the electrode pillar; an electrode layer surrounding the memory material portion and the lateral surface portion of the electrode pillar, wherein the electrode pillar, the memory material portion, and the electrode layer form a capacitive memory structure; and a field-effect transistor structure comprising a gate structure, wherein the bottom surface of the electrode pillar faces the gate structure and is electrically conductively connected to the gate structure, and wherein the top surface of the electrode pillar faces away from the gate structure.

Various aspects relate to a memory cell including: a field-effect transistor memory structure, wherein a source/drain current through the field-effect transistor memory structure is a function of a gate voltage supplied to a gate of the field-effect transistor memory structure and a memory state in which the field-effect transistor memory structure is residing in; and an access device coupled to the gate of the field-effect transistor memory structure, wherein the access device is configured to control a voltage present at the gate of the field-effect transistor memory structure.

A method of fabricating a semiconductor device includes forming a first stack of semiconductor layers on a substrate. The first stack of semiconductor layers includes alternating first and second semiconductor strips. The first and second semiconductor strips includes first and second semiconductor materials, respectively. The method also includes removing the first semiconductor strips to form voids between the second semiconductor strips in the first stack of semiconductor layers. The method further includes depositing a dielectric structure layer and a first conductive fill material in the voids to surround the second semiconductor strips. Further, the method includes removing the second semiconductor strips to form a second set of voids, and depositing a third semiconductor material in the second sets of voids.

A method of fabricating a semiconductor device includes forming a first stack of semiconductor layers on a substrate. The first stack of semiconductor layers includes alternating first and second semiconductor strips. The method also includes removing the first semiconductor strips to form voids between the second semiconductor strips in the first stack of semiconductor layers. The method further includes depositing a dielectric structure layer and a first conductive fill material in the voids to surround the second semiconductor strips. Further, the method includes removing the second semiconductor strips to form a second set of voids, and depositing a second conductive fill material in the second sets of voids. In some embodiments, the first conductive fill material and the second conductive fill material are configured to form first and second electrodes of a capacitor.

A structure includes a semiconductor substrate, a gate structure, a source/drain feature, a source/drain contact, a dielectric layer, and a ferroelectric random access memory (FERAM) structure. The gate structure is on the semiconductor substrate. The source/drain feature is adjacent to the gate structure. The source/drain contact lands on the source/drain feature. The dielectric layer spans the source/drain contact. The FeRAM structure is partially embedded in the dielectric layer and includes a bottom electrode layer on the source/drain contact and having an U-shaped cross section, a ferroelectric layer conformally formed on the bottom electrode layer, and a top electrode layer over the ferroelectric layer.

A method for fabricating a semiconductor device is provided. The method includes depositing a bottom electrode layer over a substrate; depositing a ferroelectric layer over the bottom electrode layer; depositing a first top electrode layer over the ferroelectric layer, wherein the first top electrode layer comprises a first metal; depositing a second top electrode layer over the first top electrode layer, wherein the second top electrode layer comprises a second metal, and a standard reduction potential of the first metal is greater than a standard reduction potential of the second metal; and removing portions of the second top electrode layer, the first top electrode layer, the ferroelectric layer, and the bottom electrode layer to form a memory stack, the memory stack comprising remaining portions of the second top electrode layer, the first top electrode layer, the ferroelectric layer, and the bottom electrode layer.

A memory cell circuit is provided that may include: a memory cell, the memory cell including a ferroelectric structure; a first control terminal and a second control terminal connected to the memory cell, the first control terminal and the second control terminal being configured to allow an operation of the memory cell; and a first auxiliary terminal and a second auxiliary terminal connected to the memory cell, the first auxiliary terminal and the second auxiliary terminal being configured to provide an auxiliary voltage to the ferroelectric structure.