A magnetoresistance memory device includes first, second, third and fourth ferromagnetic layers; a first and second ferromagnetic oxide layers; a metal layer; an insulating layer. The second ferromagnetic layer includes one of iron and cobalt included in the first ferromagnetic oxide layer and one element of a first element group. The second ferromagnetic oxide layer includes an oxide of an alloy of the one of iron and cobalt included in the second ferromagnetic oxide layer with a first element, which has a standard electrode potential lower than that of iron or cobalt and that of the one element of the first element group included in the second ferromagnetic layer.

According to one embodiment, a magnetic memory device includes first to third conductor layers, and a three-terminal-type memory cell connected to the first to third conductor layers. The first memory cell includes a fourth conductor layer, a magnetoresistance effect element, a two-terminal-type first switching element, and a two-terminal-type second switching element. The fourth conductor layer includes a first portion connected to the first conductor layer, a second portion connected to the second conductor layer, and a third portion which is connected to the third conductor layer. The magnetoresistance effect element is connected between the third conductor layer and the fourth conductor layer. The first switching element is connected between the second conductor layer and the fourth conductor layer. The second switching element is connected between the first conductor layer and the third conductor layer.

A magnetoresistance memory device includes a first conductor, a first insulator covering a side surface of the first conductor, a second conductor on the first conductor that are substantially made of a non-magnetic non-nitrogen material. The device includes a variable resistance material, a third conductor, a first ferromagnetic layer, an insulating layer, and a second ferromagnetic layer. The third conductor, a fourth conductor on the second ferromagnetic layer, and a second insulator covering side surfaces of the first and second ferromagnetic layers and insulating layer are substantially made of a non-nitrogen material. A third insulator is on the second insulator.

A semiconductor device that includes: first conductive lines; second conductive lines disposed over the first lines to be spaced apart from the first lines; and a selector layer disposed between the first lines and the second lines and including a dielectric material and a dopant doped with a uniform dopant profile.

A three dimensional (3D) array of magnetic random access memory (MRAM) bit-cells is described, wherein the array includes a mesh of: a first interconnect extending along a first axis; a second interconnect extending along a second axis; and a third interconnect extending along a third axis, wherein the first, second and third axes are orthogonal to one another, and wherein a bit-cell of the MRAM bit-cells includes: a magnetic junction device including a first electrode coupled to the first interconnect; a piezoelectric (PZe) layer adjacent to a second electrode, wherein the second electrode is coupled to the second interconnect; and a first layer adjacent to the PZe layer and the magnetic junction, wherein the first layer is coupled the third interconnect.

A resistance variable device of an embodiment includes a stack arranged between a first electrode and a second electrode and including a resistance variable layer and a chalcogen-containing layer. The chalcogen-containing layer contains a material having a composition represented by a general formula: C1.sub.xC2.sub.yA.sub.z, where C1 is at least one element selected from Sc, Y, Zr, and Hf, C2 is at least one element selected from C, Si, Ge, B, Al, Ga, and In, A is at least one element selected from S, Se, and Te, and x, y, and z are numbers representing atomic ratios satisfying 0<x<1, 0<y<1, 0<z<1, and x+y+z=1, and when an oxidation number of the element C1 is set to a, and an oxidation number of the element C2 is set to b, the atomic ratio x of the element C1 satisfies x≤(3−(3+b)×y−z)/(3+a).

A selector includes a first electrode, a second electrode, and a selector layer provided between the first electrode and the second electrode and contains Si.sub.xTe.sub.yN.sub.z. The x, y, and z of the Si.sub.xTe.sub.yN.sub.z satisfy 0<x≤35, 15≤y≤50, and 50<z≤85, satisfy 0<x≤45, 15≤y≤55, and 40<z≤85, or satisfy 0<x≤55, 15≤y≤65, and 30<z≤85.

According to one embodiment, a magnetoresistive memory device includes: a first conductor; a layer stack; an insulator on a side surface of the layer stack; a second conductor on a second surface of the layer stack; a third conductor; and a fourth conductor on the third conductor. The layer stack includes a first ferromagnetic layer, a second ferromagnetic layer, and an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer and has a first surface in contact with the first conductor. The second surface is at an opposite side of the first surface. The third conductor has a portion on the second conductor and a portion on a side surface of the insulator.

A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.

An integrated circuit, a system, and a method to integrate phase change memory and magnetoresistive random access memory within a same integrated circuit in a system. The integrated circuit may include an MRAM and a PCM. The MRAM may include an MRAM bottom electrode, an MRAM stack, and an MRAM top electrode. The PCM may include a PCM bottom electrode, where the PCM bottom electrode has a lower height than the MRAM bottom electrode, a phase change material, and a PCM top electrode.