According to one embodiment, a method for manufacturing a memory system that has memory cells with a variable resistance element and a switching element connected between a first wire and second wire, includes forming the variable resistance elements in the memory system in a low resistance state or a high resistance state, and then bringing each of the variable resistance elements into the low resistance state before performing either of a read operation or a write operation by performing an external initialization process that is different from the read operation and the write operation. In some examples, the variable resistance element can be a magnetoresistance type element and the external initialization process may be exposing the memory cells to an external magnetic field.

The disclosed technology relates to the field of memory devices including memory arrays, and more particularly, to magnetic memory devices. In one aspect, the disclosed technology provides a method of fabricating a memory device, and the memory device. The method comprises: processing a plurality of selector devices in a semiconductor layer of a first substrate, processing an interconnect layer on a front-side of the semiconductor layer, the interconnect layer comprising an interconnect structure electrically connected to the plurality of selector devices, processing a plurality of memory elements in an oxide layer of the first substrate arranged on a back-side of the semiconductor layer, each memory element being electrically connected to one of the selector devices, and processing one or more vias through the semiconductor layer to electrically connect the memory elements to the interconnect structure.

According to one embodiment, a magnetic memory device includes a first conductor extending along a first direction, a second conductor extending along a second direction and above the first conductor, and a first layer stack provided between the first conductor and the second conductor and including a first magnetoresistance effect element. The first layer stack has a rectangular shape along a stack surface of the first layer stack. The rectangular shape of the first layer stack has a side intersecting with both the first direction and the second direction.

A method for fabricating a semiconductor device including a plurality of memory cells. The method includes: forming a first electrode layer; forming an initial Si-containing layer over the first electrode layer; performing a radical oxidation process to covert a first portion of the initial Si-containing layer into an oxide layer including silicon dioxide (SiO.sub.2) and form a Si-containing layer under the oxide layer by using a second portion of the initial Si-containing layer; and incorporating a dopant into the oxide layer by an ion implantation process to form a selector pattern.

A memory device including a plurality of first conductive lines arranged on a substrate and spaced apart from each other in a first direction parallel to a top surface of the substrate; a plurality of capping liners on sidewalls of each of the plurality of first conductive lines, the plurality of capping liners having top surfaces at a vertical level equal to top surfaces of the plurality of first conductive lines, and bottom surfaces at a vertical level higher than bottom surfaces of the plurality of first conductive lines; and an insulating layer on the substrate, the insulating layer filling spaces between the plurality of first conductive lines and covering sidewalls of the plurality of capping liners.

A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.

An integrated circuit which enables lower cost yet provides superior performance compared to standard silicon integrated circuits by utilizing thin film transistors (TFTs) fabricated in BEOL. Improved memory circuits are enabled by utilizing TFTs to improve density and access in a three dimensional circuit design which minimizes die area. Improved I/O is enabled by eliminating the area on the surface of the semiconductor dedicated to I/O and allowing many times the number of I/O available. Improved speed and lower power are also enabled by the shortened metal routing lines and reducing leakage.

A method for fabricating an electronic device including a semiconductor memory includes: forming a memory layer over a substrate; forming a memory element by selectively etching the memory layer, wherein forming the memory element includes forming an etching residue on a sidewall of the memory element, the etching residue including a first metal; and forming a spacer by implanting oxygen and a second metal into the etching residue, the spacer including a compound of the first metal-oxygen-the second metal, the second metal being different from the first metal.

A semiconductor device that can perform product-sum operation with low power consumption is provided. The semiconductor device includes first and second circuits; the first circuit includes a first holding node and the second circuit includes a second holding node. The first circuit is electrically connected to first and second input wirings and first and second wirings, the second circuit is electrically connected to the first and second input wirings and the first and second wirings, and the first and second circuits each have a function of holding first and second potentials corresponding to first data at the first and second holding nodes. When a potential corresponding to second data is input to each of the first and second input wirings, the first circuit outputs a current to one of the first wiring and the second wiring and the second circuit outputs a current to the other of the first wiring and the second wiring. The currents output from the first and second circuits to the first wiring or the second wiring are determined in accordance with the first and second potentials held at the first and second holding nodes.

A method for fabricating an electronic device including a semiconductor memory includes: forming a variable resistance element including material layers over a substrate; forming a hard mask layer including a metal over the material layers; selectively etching the hard mask layer to form an etched hard mask layer; etching the material layers by using the etched hard mask layer as an etch barrier, the etching of the material layers providing an etch byproduct formed on sidewalls of the etched material layers and the etch byproduct including a material that is more readily oxidized than the metal of the hard mask layer; and performing a treatment using a gas or plasma to suppresses oxidation of the hard mask layer and facilitate oxidation of the etch byproducts.