A synapse device includes a perpendicularly magnetized ferrimagnetic racetrack layer, a tunneling barrier layer disposed on the racetrack layer and a reference layer including a perpendicular magnetic alloy. The racetrack layer, the tunneling layer and the reference layer have a channel portion and contact pad portions. First and second contacts are provided over the contact pad portions, and a third contact is provided over the channel portion, wherein the first and second contacts are electrically isolated from the third contact.

A magnetoresistive random access memory (MRAM) device and a method of manufacturing the same, the device including a substrate; a memory unit including a lower electrode, a magnetic tunnel junction (MTJ) structure, and an upper electrode sequentially stacked on the substrate; a passivation pattern on a sidewall of the memory unit; a via on the memory unit and contacting the upper electrode; and a wiring on the via and contacting the via, wherein a center portion of the upper electrode protrudes from a remaining portion of the upper electrode in a vertical direction substantially perpendicular to an upper surface of the substrate.

A via interconnect structure for an MRAM device is provided. The via interconnect structure includes an interlayer dielectric layer having a via formed therein, a magnetic metal layer formed in the via, the magnetic metal layer having a cavity formed therein, and a nonmagnetic metal layer formed in the cavity of the magnetic metal layer. The magnetic metal layer is configured such that magnetization vectors of the magnetic metal layer are least substantially in-plane relative to an MRAM stack structure of the MRAM device.

A magnetic memory according to an embodiment includes: a magnetic member having a cylindrical form, the magnetic member including a first end portion and a second end portion and extending in a first direction from the first end portion to the second end portion, the first end portion having an end face, which includes a face inclined with respect to a plane perpendicular to the first direction.

A method of forming a MRAM device includes forming an interconnect structure spanning a memory region and a peripheral region; forming a MTJ stack over the interconnect structure within the memory region; depositing a dielectric layer over the MTJ stack and spanning the memory region and the peripheral region; removing a first portion of the dielectric layer from the peripheral region, while leaving a second portion of the dielectric layer within the memory region; after removing the first portion of the dielectric layer from the peripheral region, forming a first IMD layer spanning the memory region and the peripheral region; forming a dual damascene structure through the first IMD layer to a metallization pattern of the interconnect structure within the peripheral region; and after forming the dual damascene structure within the peripheral region, forming a top electrode via in contact with a top electrode of the MTJ stack.

A magnetic memory device includes an MTJ element between a bottom electrode layer and a top electrode layer. The MTJ element comprises a reference layer, a tunnel barrier layer and a free layer. The reference layer comprises sub-layers that protrude beyond a sidewall of the tunnel barrier layer. The tunnel barrier layer protrudes beyond a sidewall of one of sub-layers of the free layer. Sidewall spacers are disposed to respectively cover a sidewall of the top electrode layer, sidewalls of the sub-layers of the free layer, a sidewall of the tunnel barrier layer, and sidewalls of the sub-layers of the reference layer. The etching of the MTJ stack and the formation of the sidewall spacers are carried out in the same HDPCVD chamber without breaking the vacuum.

The present invention is directed to a perpendicular magnetic structure including a seed layer structure that includes a first seed layer comprising a metal element and oxygen, and a second seed layer formed on top of the first seed layer and comprising chromium. The metal element is one of titanium, tantalum, or magnesium. The perpendicular magnetic structure further includes a magnetic fixed layer structure formed on top of the seed layer structure and having an invariable magnetization direction substantially perpendicular to a layer plane of the magnetic fixed layer structure. The magnetic fixed layer structure includes layers of a magnetic material interleaved with layers of a transition metal. The magnetic material includes cobalt. The transition metal is one of nickel, platinum, palladium, or iridium.

An exemplary method that forms spacer stacks with metallic compound layers is disclosed. The method includes forming magnetic tunnel junction (MTJ) structures on an interconnect layer and depositing a first spacer layer over the MTJ structures and the interconnect layer. The method also includes disposing a second spacer layer—which includes a metallic compound—over the first spacer material, the MTJ structures, and the interconnect layer so that the second spacer layer is thinner than the first spacer layer. The method further includes depositing a third spacer layer over the second spacer layer and between the MTJ structures. The third spacer is thicker than the second spacer.

A method includes: providing a modulation circuit, determined an operation mode of a memory array, providing a first voltage corresponding to a positive temperature coefficient in response to a read operation of the memory array, and providing a second voltage corresponding to a negative temperature coefficient in response to a write operation of the memory array. The modulation circuit is configured to generate a temperature-dependent voltage and provide the same to the memory array.

A semiconductor device including a semiconductor substrate and an interconnect structure is provided. The semiconductor substrate includes a transistor, wherein the transistor has a source region and a drain region. The interconnect structure is disposed over the semiconductor substrate, wherein the interconnect structure includes a plurality of interlayer dielectric layers, a first via and a memory cell. The plurality of interlayer dielectric layers are over the semiconductor substrate. The first via is embedded in at least two interlayer dielectric layers among the plurality of interlayer dielectric layers and electrically connected with the drain region of the transistor. The memory cell is disposed over the at least two interlayer dielectric layers among the plurality of interlayer dielectric layers and electrically connected with the first via.