Disclosed herein are related to a memory cell including magnetic tunneling junction (MTJ) devices. In one aspect, the memory cell includes a first layer including a first transistor and a second transistor. In one aspect, the first transistor and the second transistor are connected to each other in a cross-coupled configuration. A first drain structure of the first transistor may be electrically coupled to a first gate structure of the second transistor, and a second drain structure of the second transistor may be electrically coupled to a second gate structure of the first transistor. In one aspect, the memory cell includes a second layer including a first MTJ device electrically coupled to the first drain structure of the first transistor and a second MTJ device electrically coupled to the second drain structure of the second transistor. In one aspect, the second layer is above the first layer.

A composite recording structure comprising a first magnetic free layer comprising an amorphous magnetic material sub-layer, a Boron-absorbing material sub-layer atop the amorphous magnetic material sub-layer and a Co/Ni superlattice sub-layer atop the Boron-absorbing material sub-layer; one or many repeats of a substructure including a nonmagnetic spacing layer and a Co/Ni superlattice free layer, atop the first magnetic free layer, wherein said first magnetic free layer has a perpendicular magnetic anisotropy and a variable magnetization direction substantially perpendicular to a film surface, said each Co/Ni superlattice free layer has a perpendicular magnetic anisotropy and a variable magnetization direction substantially perpendicular to a film surface.

A semiconductor structure and a method for forming a semiconductor structure are provided. A substrate having a cell region and a mark region is received. A dielectric layer is etched to expose a conductive line in the cell region and form a trench in the mark region. A conductive layer is formed over the cell region and in the trench. The conductive layer is etched to form a bottom electrode via in the cell region and a first mark layer in the trench.

A magnetic memory according to en embodiment includes: a first and second wirings; an insulator portion; a magnetic member including: a first portion electrically connected to the first wiring; a second portion electrically connected to the second wiring; and a third portion disposed between the first and second portions, the magnetic member extending in a first direction from the first portion toward the second portion and surrounding the insulator portion, and in a cross-section parallel to the first direction and including part of the magnetic member and part of the insulator portion, a curvature of the first portion being smaller than a curvature of the third portion, a length of the first portion in the first direction being greater than half a length of the third portion in the first direction; and a control circuit electrically connected to the first and second wirings.

According to one embodiment, a magnetic memory device includes a stacked structure including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, a non-magnetic layer provided between the first magnetic layer and the second magnetic layer, and an oxide layer provided adjacent to the first magnetic layer, the first magnetic layer being provided between the non-magnetic layer and the oxide layer, and the oxide layer containing a rare earth element, boron (B), and oxygen (O).

Semiconductor structures and methods for manufacturing the same are provided. The method includes forming a bottom electrode layer over a substrate and forming a pinned layer over the bottom electrode layer. The method also includes forming a tunnel barrier layer over the pinned layer and forming a free layer over the tunnel barrier layer. The method also includes patterning the free layer, the tunnel barrier layer, and the pinned layer to form a magnetic tunnel junction (MTJ) stack structure and patterning the bottom electrode layer to form a bottom electrode structure under the MTJ stack structure. In addition, patterning the free layer includes using a first etching gas, and patterning the bottom electrode layer includes using a second etching gas, which is different from the first etching gas.

A semiconductor device is provided. The semiconductor device includes a base layer, a first MRAM device formed on the base layer, and a second MRAM device formed on the base layer. The first MRAM device has a different performance characteristic than the second MRAM device.

A variable resistance memory device is provided including a plurality of lower electrodes disposed on a substrate. A plurality of variable resistors are disposed on the plurality of lower electrodes. A plurality of upper electrodes are disposed on the plurality of variable resistors. An interlayer insulating layer fills a space in the plurality of variable resistors. An anti-oxidation layer is disposed between the plurality of variable resistors and the interlayer insulating layer. The anti-oxidation layer covers side surfaces of the plurality of variable resistors, and the anti-oxidation layer comprises silicon and/or carbon.

A magnetic memory structure includes a heavy-metal layer, a plurality of magnetic tunneling junction (MTJ) layer, a conductive layer and an insulation layer. In an example, the pinned-layer of the MTJ layers are arranged in a string form and disposed over the barrier-layer. In an example also disclosed, the pinned-layer, the free-layer of the MTJ layers are arranged in a string form. Whereas the pinned-layers are disposed over the barrier-layer and the free-layers are disposed over the heavy-metal layer. The conductive layer is formed under the heavy-metal layer and includes a first conductive portion and a second conductive portion separated from each other and connected with two end of the heavy-metal layer respectively. The insulation layer fills up an interval between the first conductive portion and the second conductive portion. The conductive layer has an electric conductivity higher than that of the heavy-metal layer.

The present disclosure provides a semiconductor structure including a first electrode via, a first electrode on the first electrode via, a magnetic tunneling junction (MTJ) over the first electrode, a second electrode over the MTJ, a first dielectric layer on the first electrode via, a second dielectric layer on the first dielectric layer. The first dielectric layer is a planar layer. A sidewall of the MTJ is in contact with the second dielectric layer, and a bottom surface of the second dielectric layer is higher than a bottom surface of the first electrode.