A memory device of embodiments includes: a semiconductor layer extending in a first direction; a gate electrode layer containing a first material or a second material, the first material containing tantalum (Ta), tungsten (W), and nitrogen (N), an atomic concentration of nitrogen being less than a sum of an atomic concentration of tantalum and an atomic concentration of tungsten, the second material containing niobium (Nb), molybdenum (Mo), and nitrogen (N), and an atomic concentration of nitrogen being less than a sum of an atomic concentration of niobium and an atomic concentration of molybdenum; a charge storage layer provided between the semiconductor layer and the gate electrode layer; a first insulating layer provided between the semiconductor layer and the charge storage layer; and a second insulating layer provided between the charge storage layer and the gate electrode layer.

A memory device of embodiments includes: a semiconductor layer extending in a first direction; a gate electrode layer containing a first material or a second material, the first material containing tantalum (Ta), tungsten (W), and nitrogen (N), an atomic concentration of nitrogen being less than a sum of an atomic concentration of tantalum and an atomic concentration of tungsten, the second material containing niobium (Nb), molybdenum (Mo), and nitrogen (N), and an atomic concentration of nitrogen being less than a sum of an atomic concentration of niobium and an atomic concentration of molybdenum; a charge storage layer provided between the semiconductor layer and the gate electrode layer; a first insulating layer provided between the semiconductor layer and the charge storage layer; and a second insulating layer provided between the charge storage layer and the gate electrode layer.

A phase-change memory structure includes lower and upper electrodes spaced apart from each other, and a phase-change material stack between the lower and upper electrodes. The phase-change material stack includes a plurality of phase-change layers, at least two phase-change layers of the plurality of phase-change layers have different phase-change temperatures, and a plurality of barrier layers between the plurality of phase-change layers The at least two phase-change layers of the plurality of phase-change layers have different thicknesses.

A phase-change memory structure includes lower and upper electrodes spaced apart from each other, and a phase-change material stack between the lower and upper electrodes. The phase-change material stack includes a plurality of phase-change layers, at least two phase-change layers of the plurality of phase-change layers have different phase-change temperatures, and a plurality of barrier layers between the plurality of phase-change layers The at least two phase-change layers of the plurality of phase-change layers have different thicknesses.

Various embodiments of the present application are directed toward an integrated chip (IC). The IC comprises a dielectric structure disposed over a substrate. A phase change material (PCM) structure is disposed over the dielectric structure. A first conductive structure and a second conductive structure are disposed over and electrically coupled to the PCM structure. A heating structure is disposed in the dielectric structure and laterally between the first conductive structure and the second conductive structure. The heating structure has a first surface and a second surface opposite the first surface. The first surface faces the PCM structure. The first surface has a first width and the second surface has a second width that is greater than the first width.

Various embodiments of the present application are directed toward an integrated chip (IC). The IC comprises a dielectric structure disposed over a substrate. A phase change material (PCM) structure is disposed over the dielectric structure. A first conductive structure and a second conductive structure are disposed over and electrically coupled to the PCM structure. A heating structure is disposed in the dielectric structure and laterally between the first conductive structure and the second conductive structure. The heating structure has a first surface and a second surface opposite the first surface. The first surface faces the PCM structure. The first surface has a first width and the second surface has a second width that is greater than the first width.

A phase change memory cell including: a first layer in a phase change material; a heating element located under the first layer; a second insulating layer coating a side of the heating element; and first stack comprising a third encapsulation layer coating the side faces of the second layer and a fourth encapsulation layer coating the third layer and being in a material having a lower density than that of the material of the third layer.

A phase change memory cell including: a first layer in a phase change material; a heating element located under the first layer; a second insulating layer coating a side of the heating element; and first stack comprising a third encapsulation layer coating the side faces of the second layer and a fourth encapsulation layer coating the third layer and being in a material having a lower density than that of the material of the third layer.

According to one embodiment, a cell block includes memory cells and select transistors. The memory cells correspond are connected in parallel between a local source line and a local bit line. The select transistor is connected between the local bit line and a bit line. The memory cell includes a cell transistor and a resistance change element. A gate of the cell transistor is connected to a word line. The resistance change element is connected to the cell transistor in series between the local source line and the local bit line. Each cell block is configured as a columnar structure penetrating a plurality of conductive films functioning as word lines. The select transistor and the local bit line are connected at a contact portion formed of a material different from a material of the local bit line.

According to one embodiment, a cell block includes memory cells and select transistors. The memory cells correspond are connected in parallel between a local source line and a local bit line. The select transistor is connected between the local bit line and a bit line. The memory cell includes a cell transistor and a resistance change element. A gate of the cell transistor is connected to a word line. The resistance change element is connected to the cell transistor in series between the local source line and the local bit line. Each cell block is configured as a columnar structure penetrating a plurality of conductive films functioning as word lines. The select transistor and the local bit line are connected at a contact portion formed of a material different from a material of the local bit line.