According to one embodiment, a nonvolatile semiconductor memory includes a first electrode and a second electrode spaced from the first electrode. A memory element and a switching element are disposed between the first electrode and the second electrode. The switching element includes a tunnel insulating film enabling carrier tunneling, and the tunnel insulating film includes yttrium and oxygen and at least one of tantalum, titanium, and zirconium Ti, and Zr.

According to one embodiment, a nonvolatile semiconductor memory includes a first electrode and a second electrode spaced from the first electrode. A memory element and a switching element are disposed between the first electrode and the second electrode. The switching element includes a tunnel insulating film enabling carrier tunneling, and the tunnel insulating film includes yttrium and oxygen and at least one of tantalum, titanium, and zirconium Ti, and Zr.

Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line stack extending in a first direction, the lower line stack comprising a sacrificial line over a lower conductive line. The method further includes forming a chalcogenide line extending in the first direction by selectively removing the sacrificial material of the sacrificial line and replacing the sacrificial line with a chalcogenide material.

Various 3D memory cells, array structures, and processes are disclosed. In an embodiment, a 3D memory cell structure includes a vertical conductor core, an insulator surrounding the vertical conductor core, a semiconductor layer surrounding the insulator, charge trapping layers surrounding the semiconductor layer, and a word line layer surrounding at least a portion of the charge trapping layers.

Various 3D cells, array structures and processes are disclosed. In an embodiment, a memory cell structure is provided that includes a vertical bit line, an insulator surrounding a first portion of vertical bit line, a continuous semiconductor layer surrounding the insulator and a second portion of the vertical bit line, and an extended portion of conductor material surrounding the continuous semiconductor layer. The memory cell structure also includes a first dielectric layer surrounding extended portion of conductor material, a first conductor layer surrounding the first dielectric layer, a second conductor layer surrounding the first conductor layer, a second dielectric layer on a top surface of the first and second conductor layers, a third dielectric layer on a bottom surface of the first and second conductor layers, a first gate on a top surface of the second dielectric layer, and a second gate on a bottom surface of the third dielectric layer.

Various 3D cells, array structures and processes are disclosed. In an embodiment, a memory cell structure is provided that includes a vertical bit line, an insulator surrounding a first portion of vertical bit line, a continuous semiconductor layer surrounding the insulator and a second portion of the vertical bit line, and an extended portion of conductor material surrounding the continuous semiconductor layer. The memory cell structure also includes a first dielectric layer surrounding extended portion of conductor material, a first conductor layer surrounding the first dielectric layer, a second conductor layer surrounding the first conductor layer, a second dielectric layer on a top surface of the first and second conductor layers, a third dielectric layer on a bottom surface of the first and second conductor layers, a first gate on a top surface of the second dielectric layer, and a second gate on a bottom surface of the third dielectric layer.

An example phase change memory, as well as an electronic device comprising an example phase change memory, include a plurality of phase change memory cells. Each of the plurality of phase change memory cells includes a first electrode, a phase change body, and a second electrode, which are sequentially arranged in a first direction. The phase change body has a first end face facing the first electrode and a second end face facing the second electrode. The phase change body further includes a convergence portion, and the convergence portion is located between the first end face and the second end face, where a sectional area of the convergence portion in a direction perpendicular to the first direction is relatively smaller than an area of the first end face and an area of the second end face. A preparation method for a phase change memory is also provided.

A memory cell includes a memory device, a connecting structure, an insulating layer and a selector. The connecting structure is disposed on and electrically connected to the memory device. The insulating layer covers the memory device and the connecting structure. The selector is located on and electrically connected to the memory device, where the selector is disposed on the insulating layer and connected to the connecting structure by penetrating through the insulating layer.

A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.

Provided is a phase change RAM. The phase change RAM includes an electrode, a first layer located on the electrode, and a second layer located on the first layer. The first layer includes a locally formed phase change material region. In addition, a method of manufacturing a phase change RAM is provided. The method includes forming an electrode, forming a first layer on the electrode, forming a second layer on the first layer, and forming a phase change material region locally in the first layer due to a voltage applied to the second layer.