Provided is a phase change RAM. The phase change RAM includes an electrode, a first layer located on the electrode, and a second layer located on the first layer. The first layer includes a locally formed phase change material region. In addition, a method of manufacturing a phase change RAM is provided. The method includes forming an electrode, forming a first layer on the electrode, forming a second layer on the first layer, and forming a phase change material region locally in the first layer due to a voltage applied to the second layer.

A method of manufacturing an electronic chip includes the following successive steps: a) forming of a first layer on top of and in contact with a second semiconductor layer, the second layer being on top of and in contact with a third semiconductor layer; b) doping of the first layer to form, on the second layer, a first doped sub-layer of the first conductivity type and a second doped sub-layer of the second conductivity type; c) forming of islands in the first layer organized in an array of rows and of columns at the surface of the second layer; and d) forming of memory cells based on a phase-change material on the islands of the first layer.

A method of manufacturing an electronic chip includes the following successive steps: a) forming of a first layer on top of and in contact with a second semiconductor layer, the second layer being on top of and in contact with a third semiconductor layer; b) doping of the first layer to form, on the second layer, a first doped sub-layer of the first conductivity type and a second doped sub-layer of the second conductivity type; c) forming of islands in the first layer organized in an array of rows and of columns at the surface of the second layer; and d) forming of memory cells based on a phase-change material on the islands of the first layer.

Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.

Methods, systems, and devices for chalcogenide memory device compositions are described. A memory cell may use a chalcogenide material having a composition as described herein as a storage materials, a selector materials, or as a self-selecting storage material. A chalcogenide material as described herein may include a sulfurous component, which may be completely sulfur (S) or may be a combination of sulfur and one or more other elements, such as selenium (Se). In addition to the sulfurous component, the chalcogenide material may further include one or more other elements, such as germanium (Ge), at least one Group-III element, or arsenic (As).

Methods, systems, and devices for chalcogenide memory device compositions are described. A memory cell may use a chalcogenide material having a composition as described herein as a storage materials, a selector materials, or as a self-selecting storage material. A chalcogenide material as described herein may include a sulfurous component, which may be completely sulfur (S) or may be a combination of sulfur and one or more other elements, such as selenium (Se). In addition to the sulfurous component, the chalcogenide material may further include one or more other elements, such as germanium (Ge), at least one Group-III element, or arsenic (As).

The disclosure provides a transistor array and a method for manufacturing the same, and a semiconductor device and a method for manufacturing the same. The method for manufacturing a transistor array may include the following operations. A wafer is provided. The wafer is partially etched from a first surface of the wafer along a first direction, to form a grid-like etched trench and a transistor pillar array, here the transistor pillar array includes multiple transistor pillars arranged in an array, each of the multiple transistor pillars has a first preset thickness smaller than an initial thickness of the wafer. An insulating material is deposited in the grid-like etched trench to form an insulating layer surrounding each of the multiple transistor pillars. The insulating layer is etched to expose a first sidewall and a second sidewall, opposite to each other in a second direction, of each of the multiple transistor pillars.

The disclosure provides a transistor array and a method for manufacturing the same, and a semiconductor device and a method for manufacturing the same. The method for manufacturing a transistor array may include the following operations. A wafer is provided. The wafer is partially etched from a first surface of the wafer along a first direction, to form a grid-like etched trench and a transistor pillar array, here the transistor pillar array includes multiple transistor pillars arranged in an array, each of the multiple transistor pillars has a first preset thickness smaller than an initial thickness of the wafer. An insulating material is deposited in the grid-like etched trench to form an insulating layer surrounding each of the multiple transistor pillars. The insulating layer is etched to expose a first sidewall and a second sidewall, opposite to each other in a second direction, of each of the multiple transistor pillars.

In certain aspects, a semiconductor device includes a vertical transistor, a metal bit line, and a pad layer. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body. The gate structure includes a gate dielectric and a gate electrode. The metal bit line extends in a second direction perpendicular to the first direction and coupled to a terminal of the vertical transistor via an ohmic contact. The pad layer is positioned between the gate electrode and the metal bit line in the first direction. The gate dielectric and the pad layer have different dielectric materials.

In certain aspects, a semiconductor device includes a vertical transistor, a metal bit line, and a pad layer. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body. The gate structure includes a gate dielectric and a gate electrode. The metal bit line extends in a second direction perpendicular to the first direction and coupled to a terminal of the vertical transistor via an ohmic contact. The pad layer is positioned between the gate electrode and the metal bit line in the first direction. The gate dielectric and the pad layer have different dielectric materials.