A field effect transistor may include an active layer containing an oxide compound material of at least two atomic elements including a first element of tin and a second element selected from Ge, Si, P, S, F, Ti, Cs, and Na and located over a substrate. The field effect transistor may further include a gate dielectric located on the active layer, a gate electrode located on the gate dielectric, and a source contact structure and a drain contact structure contacting a respective portion of the active layer. The oxide compound material may include at least germanium and tin. The oxide compound semiconductor material may be used as a p-type semiconductor material in BEOL structures.

A method includes applying a first voltage pulse across a memory cell, wherein the memory cell includes a selector, wherein the first voltage pulse switches the selector into an on-state; after applying the first voltage pulse, applying a second voltage pulse across the memory cell, wherein before applying the second voltage pulse the selector has a first voltage threshold, wherein after applying the second voltage pulse the selector has a second voltage threshold that is less than the first voltage threshold; and after applying the second voltage pulse, applying a third voltage pulse across the memory cell, wherein the third voltage pulse switches the selector into an on-state; wherein the selector remains continuously in an off-state between the first voltage pulse and the third voltage pulse.

A method for fabricating memory device includes: providing a substrate having a bottom electrode layer therein, forming a buffer layer and a mask layer on the buffer layer over the substrate, in contact with the bottom electrode layer, performing an advanced oxidation process on a sidewall of the buffer layer to form a resistive layer, which surrounds the whole sidewall of the buffer layer and extends upward vertically from the substrate, and forming, over the substrate, a noble metal layer and a top electrode layer on the noble metal layer, fully covering the resistive layer and the mask layer.

A method includes forming a first electrode layer over a substrate, forming an ovonic threshold switch (OTS) material layer over the first electrode layer, microwave annealing the OTS material layer, and forming a second electrode layer over the OTS material layer.

A semiconductor storage device controls writing in a memory unit including an anti-fuse element. The device includes a comparison unit configured to compare, with a reference voltage, a voltage generated across a resistor element connected in series with a power supply line used to energize the anti-fuse element, and a control unit configured to, in writing in the memory unit, control writing in the anti-fuse element of the memory unit based on an output of the comparison unit.

A semiconductor storage device controls writing in a memory unit including an anti-fuse element. The device includes a comparison unit configured to compare, with a reference voltage, a voltage generated across a resistor element connected in series with a power supply line used to energize the anti-fuse element, and a control unit configured to, in writing in the memory unit, control writing in the anti-fuse element of the memory unit based on an output of the comparison unit.

A chalcogenide material according to one embodiment includes germanium (Ge); arsenic (As); sulfur (S); selenium (Se), and at least one group III metal selected from indium (In), gallium (Ga), and aluminum (Al), wherein the content of the Ge may be greater than about 10 at % and less than or equal to about 30 at %, the content of the As may be greater than about 30 at % and less than or equal to about 50 at %, the content of Se is greater than about 20 at % and less than or equal to about 60 at %, the content of S is greater than about 0.5 at % and less than or equal to about 10 at %, and the content of the group III metal may be in the range of 0.5 at % to 10 at %.

A Cu-doped Sb.sub.2Te.sub.3 system phase change material, a phase change memory, and a preparation method thereof belonging to the technical field of micro-nano electronics are provided. A Sb—Te system phase change material is doped with Cu element to form Cu.sub.3Te.sub.2 bonds with both tetrahedral and octahedral structures in the case of local enrichment of Cu. The strongly bonded tetrahedral structure improves the amorphous stability and data retention capability of the Sb—Te system phase change material, and the octahedral structure of the crystal configuration improves the crystallization speed of the Sb—Te system phase change material. A phase change memory including the phase change material and a preparation method of the phase change material are also provided. Through the phase change material provided by the invention, both the speed and amorphous stability of the device are improved, and the comprehensive performance of the phase change memory is also enhanced.

A Cu-doped Sb.sub.2Te.sub.3 system phase change material, a phase change memory, and a preparation method thereof belonging to the technical field of micro-nano electronics are provided. A Sb—Te system phase change material is doped with Cu element to form Cu.sub.3Te.sub.2 bonds with both tetrahedral and octahedral structures in the case of local enrichment of Cu. The strongly bonded tetrahedral structure improves the amorphous stability and data retention capability of the Sb—Te system phase change material, and the octahedral structure of the crystal configuration improves the crystallization speed of the Sb—Te system phase change material. A phase change memory including the phase change material and a preparation method of the phase change material are also provided. Through the phase change material provided by the invention, both the speed and amorphous stability of the device are improved, and the comprehensive performance of the phase change memory is also enhanced.

A memory device includes two word-line electrodes, two source-line electrodes, and two data storage features for use by four memory cells, which are referred to as first, second, third and fourth memory cells. One word-line electrode is common to the first and second memory cells, and the other word-line electrode is common to the third and fourth memory cells. One source-line electrode is common to the first and second memory cells, and the other source-line electrode is common to the third and fourth memory cells. One data storage feature is common to the first and third memory cells, and the other data storage feature is common to the second and fourth memory cells.