A variable resistance memory device includes a plurality of first conductive layer pattern, a plurality of second conductive layer patterns over the first conductive layer patterns, and a plurality of lower cell structures including a switching element and a variable resistance element, the lower cell structures being formed at intersections at which the first conductive layer patterns and the second conductive layer patterns overlap each other. The first conductive layer patterns, the second conductive layer patterns and the lower cell structures serves as one of a memory cell, a first dummy pattern structure and a second dummy pattern structure. The first dummy pattern structure is formed on both edge portions in the first direction, and the second conductive layer pattern of the first dummy pattern structure protrudes in the first direction from a sidewall of the lower cell structure thereunder, and the second dummy pattern structure is formed on both edge portions in the second direction, and the first conductive layer pattern of the second dummy pattern structure protrudes in the second direction from a sidewall of the lower cell structure thereon. Failures of the variable resistance memory device due to the etch residue may decrease.

The present invention is directed to a memory device including a memory cell coupled to two wiring lines at two ends thereof. The memory cell includes a memory element, which includes a magnetic free layer and a magnetic reference layer with a tunnel junction layer interposed therebetween, and a bi-directional two-terminal selector element having multiple threshold voltages coupled to the memory element in series. The magnetic free layer has a variable magnetization direction substantially perpendicular to a layer plane thereof and the magnetic reference layer has a fixed magnetization direction substantially perpendicular to a layer plane thereof. In an embodiment, the bi-directional two-terminal selector element includes two selector devices with each selector device including two electrodes with a switching layer interposed therebetween. In another embodiment, the bi-directional two-terminal selector element includes a selector device incorporating therein two switching layers.

A switch device includes a first electrode, a second electrode, and a switch layer. The second electrode is disposed to face the first electrode. The switch layer is provided between the first electrode and the second electrode. The switch layer contains an amorphous material made of at least germanium (Ge) and one of nitrogen (N) and oxygen (O).

A memory device includes at least one memory cell which contains a resistive memory element having a conductive metal oxide located between a first electrode and a second electrode. The conductive metal oxide has a concentration of free electrons in thermodynamic equilibrium in a range from 1.0×10.sup.20/cm.sup.3 to 1.0×10.sup.21/cm.sup.3. A method of operating the memory device includes redistributing electron density to set and reset the device. An oxide barrier layer may be located between the conductive metal oxide and the second electrode.

A selector device for a memory cell in a memory array may include a first electrode, and a separator that include a first region of a single-composition layer of a mixed ionic-electronic conduction material with a first concentration of defects; and a second region of a single-composition layer of a transitional metal oxide with a second concentration of defects that is different from the first concentration of defects. The selector device may also include a second electrode, where the separator is between the first electrode and the second electrode.

An electronic device includes a semiconductor memory that includes: a first conductive pattern disposed over a substrate; a first selection element layer disposed over the first conductive pattern and having one or more first grooves therein, the first grooves overlapping the first conductive pattern; a first variable resistance layer whose sidewalls and bottom are surrounded by the first selection element layer, the first variable resistance layer being buried in the first groove; and a second conductive pattern that overlaps the first variable resistance layer and is disposed over the first variable resistance layer

Some embodiments include memory structures having a diode over a memory cell. The memory cell can include programmable material between a pair of electrodes, with the programmable material containing a multivalent metal oxide directly against a high-k dielectric. The diode can include a first diode electrode directly over one of the memory cell electrodes and electrically coupled with the memory cell electrode, and can include a second diode electrode laterally outward of the first diode electrode and not directly over the memory cell. Some embodiments include memory arrays comprising the memory structures, and some embodiments include methods of making the memory structures.

An electronic device with improved variable resistance characteristics and a method for fabricating the same are provided. In an embodiment of the disclosed technology, a method for forming an electronic device with a semiconductor memory includes forming a crystalized doped layer over a substrate; forming a barrier layer over the doped layer; forming a metal layer over the barrier layer; and reacting the barrier layer with a portion of the metal layer. The electronic device and the method of fabricating the same according to embodiments of the disclosed technology may have improved variable resistance characteristics.

A resistive memory device includes a first stacked structure and a second stacked structure. The first stacked structure includes a first bottom electrode, a first top electrode disposed on the first bottom electrode, and a first variable resistance layer disposed between the first bottom electrode and the first top electrode in a vertical direction. The second stacked structure includes a second bottom electrode, a second top electrode disposed on the second bottom electrode, and a second variable resistance layer disposed between the second bottom electrode and the second top electrode in the vertical direction. A thickness of the first variable resistance layer is less than a thickness of the second variable resistance layer for increasing the number of switchable resistance states of the resistive memory device.

A two-terminal device comprises a bottom electrode. A device element is formed upon the bottom electrode. The two-terminal device also comprises a top electrode that is formed upon the device element. The bottom electrode and the top electrode are aligned. The bottom electrode and top electrode also have a same width and depth.