A stacked phase change memory structure having a cross-point architecture is provided. The stacked phase change memory structure includes at least two phase change material element-containing structures stacked one atop the other. Each phase change material element-containing structure of the plurality of phase change material element-containing structures has a cross-point architecture and includes, from bottom to top, at least one bottom electrode, a phase change material element, and a top electrode.

A semiconductor device may include: first conductive lines; second conductive lines disposed on the first conductive lines to be spaced apart from the first conductive lines; selector layer disposed between the first conductive lines and the second conductive lines; a variable resistance layer disposed between the first conductive lines and the second conductive lines; and a first electrode layer including graphene and disposed between the variable resistance layer and the selector layer.

A variable resistance memory device includes a substrate, a first conductive line on the substrate, the first conductive line extending in a first horizontal direction, a second conductive line extending on the first conductive line in a second horizontal direction perpendicular to the first horizontal direction, and a memory cell at an intersection between the first conductive line and the second conductive line, the memory cell having a selection element layer, an intermediate electrode layer, and a variable resistance layer, and the variable resistance layer having a shape of stairs with a concave center.

A crystallization seed layer in a substrate, a phase change material layer, the phase change material layer includes a similar lattice constant as a lattice constant of the crystallization seed layer, a top electrode adjacent to a first vertical side surface and a bottom electrode adjacent to a second vertical side surface of the phase change material layer. A plurality of memory structures configured in a crossbar array, each including a crystallization seed layer, a phase change material layer above, a top electrode adjacent to a first vertical side surface and a bottom electrode adjacent to a second vertical side surface of the phase change material layer. A method including forming a crystallization seed layer, forming a phase change material layer, forming a top electrode and a bottom electrode on the substrate, each adjacent to a vertical side surface of the phase change material layer.

The present disclosure relates to an integrated circuit. The integrated circuit has a plurality of bit-line stacks disposed over a substrate and respectively including a plurality of bit-lines stacked onto one another. A data storage structure is over the plurality of bit-line stacks and a selector is over the data storage structure. A word-line is over the selector. The selector is configured to selectively allow current to pass between the plurality of bit-lines and the word-line. The plurality of bit-line stacks include a first bit-line stack, a second bit-line stack, and a third bit-line stack. The first and third bit-line stacks are closest bit-line stacks to opposing sides of the second bit-line stack. The second bit-line stack is separated from the first bit-line stack by a first distance and is further separated from the third bit-line stack by a second distance larger than the first distance.

A memory cell includes a first diode, a second diode, and a random access memory cell element. The first diode and the random access memory cell element are series connected between a bit line and a word line. The second diode and the random access memory cell element are series connected between the word line and a reset line. A set path is formed through the first diode and the random access memory cell element, and a reset path is formed through the random access memory cell element and the second diode. The first diode is configured to performed a read operation and a set operation. The second diode is configured to perform a reset operation. The memory cell has higher forward current, lower leakage current and smaller size comparing with conventional memory cells.

The present invention is directed to a memory device that includes an array of memory cells. Each of the memory cells includes a memory element connected to a two-terminal selector element. The two-terminal selector element includes a first electrode and a second electrode with a switching layer interposed therebetween. The switching layer includes a plurality of metal-rich clusters embedded in a nominally insulating matrix. One or more conductive paths are formed in the switching layer when an applied voltage to the memory cell exceeds a threshold level. Each of the memory cells may further include an intermediate electrode interposed between the memory element and the two-terminal selector element. The two-terminal selector element may further include a third electrode formed between the first electrode and the switching layer, and a fourth electrode formed between the second electrode and the switching layer.

A method of fabricating a fin selector with a gated RRAM and the resulting device are disclosed. Embodiments include forming a bottom electrode layer and a hardmask on a semiconductor substrate; etching the hardmask, bottom electrode layer, and semiconductor substrate to form a fin-like structure; forming first and second dummy gate stacks on first and second side surfaces of the fin-like structure, respectively; forming spacers on vertical surfaces of the first and second dummy gate stacks; forming an ILD surrounding the spacers; removing the first and second dummy gate stacks, forming first and second cavities on first and second sides of the fin-like structure; forming an RRAM layer on the first and second side surfaces of the fin-like structure in the first and second cavities, respectively; and filling each of the first and second cavities with a top electrode.

In a memory cell unit array, memory cell units each constituted of first wires, second wires, and a nonvolatile memory cell are arranged in a two-dimensional matrix form in a first direction and a second direction. Each of the memory cell units includes a control circuit below it. The control circuit is constituted of a first control circuit and a second control circuit. The second wires are connected to the second control circuit. Some of the first wires that constitute the memory cell unit are connected to the first control circuit that constitutes this memory cell unit. Others of the first wires are connected to the first control circuit that constitutes an adjacent memory cell unit adjacent thereto in the first direction.

A method of manufacturing a phase change memory includes: forming a stacked structure including a conductive layer; a lower electrode layer over the conductive layer; an upper electrode layer over the lower electrode layer; and a phase change material between the lower and upper electrode layers; etching the upper electrode layer according to a first mask to form an upper electrode wire; simultaneously etching the phase change material according to the upper electrode wire and performing a nitridizing treatment in a same plasma etching chamber until a phase change material layer and a nitridized phase change material layer are formed beneath the upper electrode wire and a portion of the lower electrode layer is exposed, wherein the nitridized phase change material layer covers a side surface of the phase change material layer; and removing the portion of the lower electrode layer and the conductive layer therebeneath.