A mixed ionic electron conductor (MIEC)-based memory cell access device is provided. The MIEC-based memory cell access device includes a MIEC material portion located between a bottom electrode and a top electrode. A contact area between the MIEC material portion and the bottom electrode is substantially the same as a contact area between the MIEC material portion and the top electrode.

In one embodiment of the present invention, a resistive switching device includes a first electrode disposed over a substrate and coupled to a first potential node, a switching layer disposed over the first electrode, a conductive amorphous layer disposed over the switching layer, and a second electrode disposed on the conductive amorphous layer and coupled to a second potential node.

A three-dimensional resistive memory device includes an alternating stack of electrically conductive layers and insulating layers. Resistive memory elements are provided between the electrically conductive layers and a semiconductor local bit line. The semiconductor local bit line includes a heterostructure of an inner semiconductor material layer having an inner-material band gap and an outer semiconductor material layer having an outer-material band gap that is narrower than the inner-material band. A gate dielectric is located between a gate electrode and the inner semiconductor material layer.

In accordance with an example embodiment of the present invention, an apparatus is disclosed. The apparatus includes a resistive memory component including an active material and two or more electrodes in electrical contact with the active material of the resistive memory component; and a selector component providing control over the resistive memory component, the selector component including an active material and two or more electrodes in electrical contact with the active material of the selector component. The resistive memory component and the selector component share one or more electrodes, and the resistive memory component and the selector component share at least part of the active material. A method and apparatus for producing the apparatus are also disclosed.

A resistive memory device includes a first electrode, a memristor coupled in electrical series with the first electrode, a second electrode coupled in electrical series with the memristor, a selector coupled in electrical series with the second electrode, and a third electrode coupled in electrical series with the selector. The memristor includes oxygen or nitrogen elements. The selector includes a composite dielectric material of a first dielectric material, a second dielectric material that is different from the first dielectric material, and a dopant material including a cation having a migration rate faster than the oxygen or the nitrogen elements of the memristor. The first dielectric material and the second dielectric material are present in a ratio ranging from 1:9 to 9:1, and a concentration of the dopant material in the composite dielectric material ranges from about 1% up to 50%.

A composite selector electrode includes a switching layer coupled in electrical parallel with a conducting layer. The switching layer is electrically insulating when the temperature of the switching layer is below a threshold temperature. The switching layer exhibits insulator-metal transition at the threshold temperature. The switching layer is electrically conducting when the temperature of the switching layer is above the threshold temperature.

Provided in one example is a nonvolatile memory crossbar array. The array includes a number of junctions formed by a number of row lines intersecting a number of column lines; and a resistive memory element in series with a selector at each of the junctions coupling between one of the row lines and one of the column lines. The selector may be a volatile switch including: a bottom electrode; an oxide layer disposed over the bottom electrode, the oxide layer including Cu.sub.2O; and a top electrode disposed over the oxide layer.

A superlinear selector includes a first electrode, a second electrode, and an active layer coupled in series between the first electrode and the second electrode. The active layer includes a superlinear electrical conductor and an electrical insulator. One of the superlinear electrical conductor and the electrical insulator forms a matrix in which the other of the superlinear electrical conductor and the electrical insulator is dispersed.

A device has a M.sub.8XY.sub.6 layer in between a first conductive layer on the top and a second conductive layer on the bottom, wherein (i) M includes at least one element selected from the following: Cu, Ag, Li, and Zn, (ii) X includes at least one Group XIV element, and (iii) Y includes at least one Group XVI element. Another device has M.sub.aX.sub.bY.sub.c material contacted on opposite sides by respective layers of conductive material, wherein: (i) M includes at least one element selected from the following: Cu, Ag, Li, and Zn, (ii) X includes at least one Group XIV element, and (iii) Y includes at least one Group XVI element, and a is in the range of 48-60 atomic percent, b is in the range of 4-10 atomic percent, c is in the range of 30-45 atomic percent, and a+b+c is at least 90 atomic percent.

The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F.sup.2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.