A method of manufacturing a phase change memory includes: forming a stacked structure including a conductive layer; a lower electrode layer over the conductive layer; an upper electrode layer over the lower electrode layer; and a phase change material between the lower and upper electrode layers; etching the upper electrode layer according to a first mask to form an upper electrode wire; simultaneously etching the phase change material according to the upper electrode wire and performing a nitridizing treatment in a same plasma etching chamber until a phase change material layer and a nitridized phase change material layer are formed beneath the upper electrode wire and a portion of the lower electrode layer is exposed, wherein the nitridized phase change material layer covers a side surface of the phase change material layer; and removing the portion of the lower electrode layer and the conductive layer therebeneath.

A memory device including a first array of rail structures that extend along a first horizontal direction, in which each of the rail structures are formed to serve as a bottom electrode, and a second array of rail structures that laterally extend along a second horizontal direction and are laterally spaced apart along the first horizontal direction. Each of the rail structures in the second array are formed to server as a top electrode. The memory device also includes a continuous dielectric memory layer located between the first array of rail structures and the second array of rail structures. The continuous dielectric memory layer providing protection from current leakage between the rail structures of the first array and the rail structures of the second array.

Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected. When the number of activated memory cells matches either the predetermined number or the total number, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.

An electronic device comprising a semiconductor memory including a plurality of memory cells is provided. Each of the plurality of memory cells includes: a first electrode layer; a variable resistance layer disposed over the first electrode layer; a second electrode layer disposed over the variable resistance layer; and an interface electrode layer interposed between the first electrode layer and the variable resistance layer or between the second electrode layer and the variable resistance layer. The interface electrode layer includes a porous metal-containing layer.

A semiconductor memory includes a substrate including a cell region, a first peripheral circuit region, and a second peripheral circuit region; a plurality of first lines disposed over the substrate across the cell region and the first peripheral circuit region; a plurality of second lines disposed over the first lines across the cell region and the second peripheral circuit region; and a first memory cell positioned at each of intersections between the first lines and the second lines, wherein the cell region includes a first cell region and a second cell region, the first cell region being disposed closer to the first and second peripheral circuit regions than the second cell region, and wherein a first portion of the second line that is in the first cell region has a greater resistance than a second portion of the second line that is in the second cell region.

The disclosed technology generally relates to a memory selector and to a memory device including the memory selector, and more particularly to the memory selector and the memory device implemented in a crossbar memory architecture. In one aspect, a memory selector for a crossbar memory architecture comprises a metal bottom electrode, a metal top electrode and an intermediate layer stack between and in contact with the metal top and bottom electrodes. A bottom Schottky barrier having a bottom Schottky barrier height (Φ.sub.B) is formed at the interface between the metal bottom electrode and the intermediate layer stack. A top Schottky barrier having a top Schottky barrier height (Φ.sub.T) is formed at the interface between the metal top electrode and the intermediate layer stack. The disclosed technology further relates to a random access memory (RAM) and a memory cell including the memory selector.

Embodiments disclosed herein include semiconductor devices with Schottky diodes in a back end of line stack. In an embodiment, a semiconductor device comprises a semiconductor layer, where transistor devices are provided in the semiconductor layer, and a back end stack over the semiconductor layer. In an embodiment, a diode is in the back end stack. In an embodiment, the diode comprises a first electrode, a semiconductor region over the first electrode, and a second electrode over the semiconductor region. In an embodiment, a first interface between the first electrode and the semiconductor region is an ohmic contact, and a second interface between the semiconductor region and the second electrode is a Schottky contact.

An electronic device including a semiconductor memory is provided. The semiconductor memory includes: a plurality of lower lines disposed over a substrate and extending in a first direction; a plurality of upper lines disposed over the lower lines and extending in a second direction crossing the first direction; a plurality of memory cells disposed between the lower lines and the upper lines and overlapping intersection regions of the lower lines and the upper lines; and an air gap located between the upper lines and extending in the second direction.

A method of fabricating a three-dimensional semiconductor memory device includes forming a cell stack layer covering key and cell regions of a substrate and including a variable resistance layer and a switching layer, forming key mask patterns on the cell stack layer of the key region and cell mask patterns on the cell stack layer of the cell region, and simultaneously forming a plurality of key patterns on the key region and a plurality of memory cells on the cell region by etching the cell stack layer using the key and cell mask patterns as an etching mask. Each memory cell includes a variable resistance pattern and a switching pattern formed by etching the variable resistance layer and the switching layer. Each key pattern includes a dummy variable resistance pattern and a dummy switching pattern formed by etching the variable resistance layer and the switching layer.

A sputtering target and a method for fabricating an electronic device using the same are provided. A sputtering target may include a carbon-doped GeSbTe alloy, wherein, for the carbon-doped GeSbTe alloy, an average grain diameter of a GeSbTe alloy after sintering is in a range of 0.5 μm to 5 μm, and a first ratio of an average grain diameter of carbon after the sintering is Y (μm) to the average grain diameter of the GeSbTe alloy after the sintering may be in a range of greater than 0.5 and equal to or less than 1.5. Alternatively, for the carbon-doped GeSbTe alloy, a condition of Y=X×(Z/100) may be satisfied, where an average grain diameter of a GeSbTe alloy after sintering is X (μm), an average grain diameter of carbon after the sintering is Y (μm), and a content of carbon is Z (at %).