A three-dimensional semiconductor integrated circuit includes a first CMOS circuit layer including a plurality of first CMOS circuit blocks; an insulating layer disposed on a top of the first CMOS circuit layer; a plurality of atomic switching elements respectively disposed inside via holes extending through the insulating layer, wherein the plurality of atomic switching elements are electrically connected to the plurality of first CMOS circuit blocks, respectively; a driver circuit layer disposed on a top of the insulating layer, and electrically connected with the atomic switching elements, wherein the driver circuit layer include a driver circuit for selectively turning on and off the atomic switching elements; and a second CMOS circuit disposed on a top of the driver circuit layer and connected to the atomic switching elements.

A memory device may be provided, including a base insulating layer, a bottom electrode arranged within the base insulating layer, a substantially planar switching layer arranged over the base insulating layer and a substantially planar top electrode arranged over the switching layer in a laterally offset position relative to the bottom electrode.

The present disclosure, in some embodiments, relates to a method of forming a memory device. The method includes forming a data storage layer on a bottom electrode layer over a substrate, forming a first top electrode layer over the data storage layer, and forming a second top electrode layer over the first top electrode layer. The first top electrode layer has a smaller corrosion potential than the second top electrode layer. A first patterning process is performed on the first top electrode layer and the second top electrode layer to define a multi-layer top electrode. A second patterning process is performed on the data storage layer and the bottom electrode layer to define a data storage structure and a bottom electrode.

A resistive memory device includes a magnetic tunnel junction structure. The magnetic tunnel junction structure includes a free magnetic layer. The free magnetic layer includes a magnetic material configurable to host topological spin textures to tune a conductance state of the resistive memory device.

A manufacturing method is provided. The method includes steps below. Forming bottom electrodes. Blanketly forming a resistance switching layer on the bottom electrodes. Forming a first insulating material layer on the resistance switching layer. Patterning the first insulating material layer to form insulating patterns. Conformally forming a channel layer having a plurality of channel regions on the resistance switching layer and the insulating patterns, wherein the plurality of channel regions are located on the resistance switching layer and cover opposite sides of the insulating patterns. Forming a second electrode material layer on the channel layer. Patterning the second electrode material layer to form top electrodes, each of the top electrodes is located in corresponding to one of the insulating patterns and covers at least two of the plurality of channel regions.

A semiconductor device includes a plurality of magnetic tunnel junction (MTJ) structures in an interlayer insulating layer on a substrate. A blocking layer is on the interlayer insulating layer and the plurality of MTJ structures. An upper insulating layer is on the blocking layer. An upper interconnection is on the upper insulating layer. An upper plug is connected to the upper interconnection and a corresponding one of the plurality of MTJ structures and extends into the upper insulating layer and the blocking layer. The blocking layer includes a material having a higher absorbance constant than the upper insulating layer.

Methods, systems, and devices for techniques for forming memory structures are described. Forming a memory structure may include etching a stack of material including a conductive line, a first electrode and a sacrificial material to divide the stack of material into multiple sections. The process may further include depositing an oxide material in each of the first quantity of channels to form multiple oxide materials. The sacrificial material may be etched to form a second channel between two oxide materials of the multiple oxide materials. Memory material may be deposited over the two oxide materials and the second channel, which may create a void in the second channel between the memory material and the first electrode. The memory material may be heated to fill the void in the second channel.

A variable resistance memory device includes a variable resistance layer, a first conductive element, and a second conductive element. The variable resistance layer includes a first layer and a second layer. The first layer is formed of a first material. The second layer is on the first layer and formed of a second material having a density different from a density of the first material. The first conductive element and a second conductive element are located on the variable resistance layer and spaced apart from each other in order to form a current path in the variable resistance layer. The current path is in a direction perpendicular to a direction in which the first layer and the second layer are stacked.

Some embodiments relate to a memory device. The memory device includes a first electrode overlying a substrate. A data storage layer is disposed on the first electrode. A second electrode overlies the data storage layer. A buffer layer is disposed between the data storage layer and the second electrode.

Various embodiments of the present disclosure are directed towards a memory device. The memory device has a first transistor having a first source/drain and a second source/drain, where the first source/drain and the second source/drain are disposed in a semiconductor substrate. A dielectric structure is disposed over the semiconductor substrate. A first memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the first memory cell has a first electrode and a second electrode, where the first electrode of the first memory cell is electrically coupled to the first source/drain of the first transistor. A second memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the second memory cell has a first electrode and a second electrode, where the first electrode of the second memory cell is electrically coupled to the second source/drain of the first transistor.