A memory cell includes: a resistive material layer comprising a first portion that extends along a first direction and a second portion that extends along a second direction, wherein the first and second directions are different from each other; a first electrode coupled to a bottom surface of the first portion of the resistive material layer; and a second electrode coupled to the second portion of the resistive material layer.

Technologies for reducing series resistance are disclosed. An example method may include: forming a first layer on a temporary substrate; forming a second layer on the first layer; etching the first layer and the second layer to form a trench; electroplating a top electrode via the trench, wherein the top electrode partially formed on a top surface of the second layer; removing the first layer and the second layer; forming a curable layer on the temporary substrate and the top electrode; removing the temporary substrate from the curable layer and the top electrode; forming a cross-point device on the curable layer and the top electrode; forming a bottom electrode on the cross-point device; and forming a flexible substrate on the bottom electrode.

A method for manufacturing a semiconductor device includes forming a plurality of memory elements on a first interconnect level, and forming an etch stop layer on the plurality of memory elements. A dielectric layer is formed on the etch stop layer, and a portion of the dielectric over the plurality of memory elements is removed to expose a portion of the etch stop layer. The method further includes removing the exposed portion of the etch stop layer. The removing of the portion of the dielectric layer and of the exposed portion of the etch stop layer forms a trench. A metallization layer is formed in the trench on the plurality of memory elements, wherein the metallization layer is part of a second interconnect level.

The present disclosure provides an apparatus, including: a substrate; a bottom electrode formed on the substrate; a first base oxide layer formed on the bottom electrode; a first geometric confining layer formed on the first base oxide layer, wherein the first geometric confining layer comprises a first plurality of pin-holes; a second base oxide layer formed on the first geometric confining layer and connected to a first top surface of the first base oxide layer via the first plurality of pin-holes; and a top electrode formed on the second base oxide layer. The first base oxide layer includes TaOx, HfOx, TiOx, ZrOx, or a combination thereof. The first geometric confining layer comprises Al.sub.2O.sub.3, SiO.sub.2, Si.sub.3N.sub.4, Y.sub.2O.sub.3, Gd.sub.2O.sub.3, Sm.sub.2O.sub.3, CeO.sub.2, Er.sub.2O.sub.3, or a combination thereof.

Embodiments disclosed herein include an RRAM cell. The RRAM cell may include a first nanowire electrically connected to a first wordline electrode. The nanowire may include a first sharpened point distal from the first wordline electrode. The RRAM cell may also include a metal contact electrically connected to a bitline electrode and a high-κ dielectric layer directly between the nanowire and the metal contact.

A memory device is provided that includes a method and structure for forming a resistive memory (RRAM) which has a gradual instead of abrupt change of resistance during programming, rendering it suitable for analog computing. In a first embodiment: One electrode of the inventive RRAM comprises a metal-nitride material (e.g., titanium nitride (TiN)) with gradually changing concentration of a metal composition (e.g., titanium). Different Ti concentrations in the electrode results in different concentration of oxygen vacancy in the corresponding section of the RRAM thereby exhibiting a gradual change of resistance dependent upon an applied voltage. The total conductance of the RRAM is the sum of conductance of each section of the RRAM. In a second embodiment: a RRAM with one electrode having multiple forks of electrodes with different composition concentration and thus different switching behaviors, rendering the inventive RRAM changing conductance gradually instead of abruptly.

A storage device includes a first electrode, a second electrode, and a resistance change storage layer between the first and second electrodes. The storage layer is either in a first resistance state or in a second resistance state having a resistance higher than the first resistance state and contains at least two elements selected from a group consisting of germanium, antimony, and tellurium. The storage device further includes an interface layer between the first electrode and the resistance change storage layer. The interface layer contains at least one of the elements of the resistance change storage layer and includes a conductive region and an insulating region.

In one embodiment, a method of manufacturing a semiconductor device includes forming a first layer including a metal element on a substrate, and processing the first layer by dry etching. The method further includes removing a second layer formed on a lateral face of the first layer by wet etching, after processing the first layer, and forming a first film on the lateral face of the first layer by processing the lateral face of the first layer with a liquid, after removing the second layer. Furthermore, the substrate is not exposed to ambient air, after removing the second layer and before forming the first film.

A semiconductor device comprises a plurality of resistive memory element structures, at least a subset of the plurality of resistive memory element structures being associated with random analog resistive states. The random analog resistive states of the subset of the plurality of resistive memory element structures provide a unique identification of the semiconductor device.

A method of forming bottom electrodes in a resistive memory device, can include: depositing a bottom insulator on a substrate ILD; forming vias in the substrate by patterning and etching holes in the bottom insulator and the substrate ILD; filling the holes with a via metal to form a flat via surface; depositing a bottom electrode thin film and a top insulator; defining the bottom electrode; etching the top insulator, the bottom electrode thin film, and the bottom insulator; depositing a cell plate layer having a switching layer, an anode layer, and a cap layer; patterning the cell plate layer by depositing and patterning a cell plate hard mask layer, and then etching the cell plate layer; encapsulating the cell plate layer; and forming electrical contact to the cell plate layer.