An electronic device comprising a semiconductor memory including at least one memory element is provided. The memory element comprises: a memory area for storing data; and a selection element electrically connected to the memory area and structured to include a first electrode layer, a second electrode layer, and a selection element layer that is interposed between the first electrode layer and the second electrode layer and includes an insulating material doped with a first dopant and a second dopant to form traps for trapping charge carriers, wherein an energy level of a trap formed by the first dopant is greater than an energy level of a trap formed by the second dopant.

A cross-point memory includes a plurality of memory devices, with each device comprising a memory layer between first and second address lines. In one preferred embodiment, the memory layer comprises an OTS (Ovonic Threshold Switch) film and an antifuse film. In another preferred embodiment, the memory layer comprises an OTS film having a first switch voltage (i.e. forming voltage V.sub.form) greater than all subsequent switch voltages (i.e. threshold voltage V.sub.th). The cross-point memory is preferably a three-dimensional one-time-programmable memory (3D-OTP), including horizontal 3D-OTP and vertical 3D-OTP

A memory includes first signal lines divided into groups respectively including m (m is an integer equal to or larger than 2) lines, and second signal lines. A memory cell array includes memory cells. (m+2) or more global signal lines are configured to apply a selection voltage to any of the first signal lines. First transistors are provided to correspond to each of the first signal lines in one-to-one correspondence and are connected between the first signal lines and the global signal lines. First selection signal lines are provided to respectively correspond to the groups, and are each connected to gate electrodes of the first transistors included in a corresponding one of the groups in common. The first signal lines located at both ends of each of any two of the groups which are adjacent to each other are connected to mutually different ones of the global signal lines.

Disclosed is a semiconductor device including first conductive lines, second conductive lines crossing the first conductive lines, and memory cells at intersections between the first conductive lines and the second conductive lines. Each of the memory cells includes a magnetic tunnel junction pattern, a bi-directional switching pattern connected in series to the magnetic tunnel junction pattern, and a conductive pattern between the magnetic tunnel junction pattern and the bi-directional switching pattern.

Disclosed herein are quantum dot devices and techniques. In some embodiments, a quantum computing processing device may include a quantum well stack, an array of quantum dot gate electrodes above the quantum well stack, and an associated array of selectors above the array of quantum dot gate electrodes. The array of quantum dot gate electrodes and the array of selectors may each be arranged in a grid.

Embodiments of the present application relate to a resistive memory device and a preparation method thereof. The preparation method includes: providing a base; forming bit line trenches in the base; forming a resistive material layer on a sidewall and the bottom of the bit line trench; and forming a bit line structure in the bit line trench through filling, wherein a variable resistor structure includes the bit line structure and the resistive material layer.

A memory device includes a cell block including memory cells; a control logic; and a correction block in a dummy region in a core region. The correction block may include first metal lines extending in a first direction; vias extending in a second direction; and second metal lines extending in a third direction. Each of the second metal lines may have a metal center line defining a center of each of the second metal lines in the first direction. Each of the vias may have a via center line defining a center of each of the vias in the first direction. At least one metal center line and at least one via center line may be spaced apart from each other by a first gap in the first direction.

The problem of forming top electrode vias that provide consistent results in devices that include resistance switching RAM cells of varying heights is solved using a dielectric composite that fills areas between resistance switching RAM cells and varies in height to align with the tops of both the taller and the shorter resistance switching RAM cells. An etch stop layer may be formed over the dielectric composite providing an equal thickness of etch-resistant dielectric over both taller and shorter resistance switching RAM cells. The dielectric composite causes the etch stop layer to extend laterally away from the resistance switching RAM cells to maintain separation between the via openings and the resistance switching RAM cell sides even when the openings are misaligned.

The present disclosure includes memory cell structures and method of forming the same. One such memory cell includes a first electrode having sidewalls angled less than 90 degrees in relation to a bottom surface of the first electrode, a second electrode, including an electrode contact portion of the second electrode, having sidewalls angled less than 90 degrees in relation to the bottom surface of the first electrode, wherein the second electrode is over the first electrode, and a storage element between the first electrode and the electrode contact portion of the second electrode.

Embodiments disclosed herein may relate to forming a base contact layout in a memory device.