A circuit for performing energy-efficient and high-throughput multiply-accumulate (MAC) arithmetic dot-product operations and convolution computations includes a two dimensional crossbar array comprising a plurality of row inputs and at least one column having a plurality of column circuits, wherein each column circuit is coupled to a respective row input. Each respective column circuit includes an excitatory memristor neuron circuit having an input coupled to a respective row input, a first synapse circuit coupled to an output of the excitatory memristor neuron circuit, the first synapse circuit having a first output, an inhibitory memristor neuron circuit having an input coupled to the respective row input, and a second synapse circuit coupled to an output of the inhibitory memristor neuron circuit, the second synapse circuit having a second output. An output memristor neuron circuit is coupled to the first output and second output of each column circuit and has an output.

Various embodiments of the present disclosure are directed towards a memory cell comprising a high electron affinity dielectric layer at a bottom electrode. The high electron affinity dielectric layer is one of multiple different dielectric layers vertically stacked between the bottom electrode and a top electrode overlying the bottom electrode. Further, the high electrode electron affinity dielectric layer has a highest electron affinity amongst the multiple different dielectric layers and is closest to the bottom electrode. The different dielectric layers are different in terms of material systems and/or material compositions. It has been appreciated that by arranging the high electron affinity dielectric layer closest to the bottom electrode, the likelihood of the memory cell becoming stuck during cycling is reduced at least when the memory cell is RRAM. Hence, the likelihood of a hard reset/failure bit is reduced.

A semiconductor memory device includes a bit line extending in a first direction, a channel pattern on the bit line, the channel pattern including first and second vertical portions facing each other and a horizontal portion connecting the first and second vertical portions, first and second word lines provided on the horizontal portion and between the first and second vertical portions and extended in a second direction crossing the bit line, and a gate insulating pattern provided between the first word line and the channel pattern and between the second word line and the channel pattern.

A device structure includes at least one selector device. Each selector device includes a vertical stack including, from bottom to top, a bottom electrode, a metal oxide semiconductor channel layer, and a top electrode and located over a substrate, a gate dielectric layer contacting sidewalls of the bottom electrode, the metal oxide semiconductor channel layer, and the top electrode, and a gate electrode formed within the gate dielectric layer and having a top surface that is coplanar with a top surface of the top electrode. Each top electrode or each bottom electrode of the at least one selector device may be contacted by a respective nonvolatile memory element to provide a one-selector one-resistor memory cell.

A non-volatile memory structure, and methods of manufacture, which may include a first memory element and a second memory element between a first terminal and a second terminal. The first memory element and the second memory element may be in parallel with each other between the first and second terminal. This may enable the hybrid non-volatile memory structure to store values as a combination of the conductance for each memory element, thereby enabling better tuning of set and reset conductance parameters.

A resistive random access memory (RRAM) device includes a plurality of memory cells, each of at least a subset of the memory cells including first and second electrodes and an organic thin film compound mixed with silver perchlorate (AgClO.sub.4) salt as a base layer that is incorporated with a prescribed quantity of inorganic metal oxide molecules using vapor-phase infiltration (VPI), the base layer being formed on an upper surface of the first electrode and the second electrode being formed on an upper surface of the base layer. Resistive switching characteristics of the RRAM device are controlled as a function of a concentration of AgClO.sub.4 salt in the base layer. A variation of device switching parameters is controlled as a function of an amount of infiltrated metal oxide molecules in the base layer.

Disclosed are a method of operating a selector device, a method of operating a nonvolatile memory apparatus to which the selector device is applied, an electronic circuit device including the selector device, and a nonvolatile memory apparatus. The method of operating the selector device controls access to a memory element, and includes providing the selector device including a switching layer and first and second electrodes disposed on both surfaces of the switching layer, which includes an insulator and a metal element, and applying a multi-step voltage pulse to the switching layer via the first and second electrodes to adjust a threshold voltage of the selector device, the multi-step voltage pulse including a threshold voltage control pulse and an operating voltage pulse. The operating voltage pulse has a magnitude for turning on the selector device, and the threshold voltage control pulse has a lower magnitude lower than the operating voltage pulse.

A resistive memory device including a resistive memory pattern; and a selection element pattern electrically connected to the resistive memory pattern, the selection element pattern including a chalcogenide switching material and at least one metallic material, the chalcogenide switching material including germanium, arsenic, and selenium, and the at least one metallic material including aluminum, strontium, or indium, wherein the selection element pattern includes an inhomogeneous material layer in which content of the at least one metallic material in the selection element pattern is variable according to a position within the selection element pattern.

Methods, systems, and devices for tapered memory cell profiles are described. A tapered profile memory cell may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a bottom surface and a top surface opposite the bottom surface. In some cases, the self-selecting memory component may taper from the bottom surface to the top surface. In other examples, the self-selecting memory component may taper from the top surface to the bottom surface. The top surface of the self-selecting memory component may be coupled to a top electrode, and the bottom surface of the self-selecting memory component may be coupled to a bottom electrode.

Methods, systems, and devices for fabrication of memory cells are described. An electrode layer may have an initial thickness variation after being formed. The electrode layer may be smoothened prior to forming additional layers of a memory cell, thus decreasing the thickness variation. The subsequent layer fabricated may have a thickness variation that may be dependent on the thickness variation of the electrode layer. By decreasing the thickness variation of the electrode layer prior to forming the subsequent layer, the subsequent layer may also have a decreased thickness variation. The decreased thickness variation of the subsequent layer may impact the electrical behavior of memory cells formed from the subsequent layer. In some cases, the decreased thickness variation of the subsequent layer may allow for more predictable voltage thresholds for such memory cells, thus increasing the read windows for the memory cells.