Methods, systems, and devices for memory architectures with partially filled piers are described. A stack of materials including alternating layers of nitride and oxide may be formed, and piers and pillars may be formed through the stack of materials. Layers of nitride may be etched for metallization and one or more piers may be removed, which may result in corresponding cavities being formed in the stack of materials. Memory cells may be formed between one or more pillars and corresponding electrodes, and the cavities (e.g., the cavities resulting from removing one or more piers) may be partially filled with a dielectric material such that an air gap is formed within the cavity, or with a low-k dielectric material, or both.

Methods, systems, and devices for replacement channel integration for three dimensional memory cell architectures are described. A method of manufacturing a memory architecture may include forming a stack of materials above a substrate. Trenches may be formed within the stack of materials, where each trench may include a gate oxide material lining the trench, and pairs of conductive pillars forming gate elements. The gate elements may form word lines associated with activating memory cells of the memory architecture. Another trench may be formed perpendicular to the trenches, and used for forming memory cells each including a selection element and a storage element within sacrificial layers of the stack of materials between the trenches. The trench may form a source line for accessing the memory cells adjacent to the trench. A digit line may be formed around the trenches and may be configured to access the memory cells.

A memory device and a method for operating a memory device are provided. The memory device includes a stack structure including a memory array stack and a staircase stack, an insulating film on the memory array stack, a conductive film on the staircase stack and on a sidewall of the insulating film, a pillar element on the staircase stack and passing through the conductive film, and memory cells in the memory array stack and electrically connected to the pillar element.

A cryogenic memory device comprising: a magnetic element made of thin film material and capable of forming at least one skyrmion; a superconducting element made of thin film material and capable of forming at least one superconducting vortex; and a nonmagnetic thin film barrier material that separates at top surface of magnetic element from a bottom surface of the superconducting element so as to form a skyrmion-based nonvolatile cryogenic memory.