Described examples include an integrated circuit having a plurality of nominally identical polycrystalline silicon resistors over a semiconductor substrate. Each of the polysilicon resistors has a resistor body with a first end and a second end, wherein the first end is connected to a current source and the second end is connected to a resistance discriminator. A first proper subset of the resistors have a first resistance, and a second first proper subset of the resistors have a difference second resistance.

A light sensing and memory integrated electronic device includes a thin film transistor element and a memory element. The thin film transistor element includes a channel layer, a source layer and a drain layer. The channel layer is made of a transparent oxide. The memory element is on the source layer. The memory element includes a lower metal layer, a dielectric layer, a matching metal layer, and an upper metal layer stacked in sequence from bottom to top, where the lower metal layer is connected to the source layer. The light sensing and memory integrated electronic device provides a single device to perform light sensing, memorizing, and generating a spike-form signal required by a neural network. It can simplify a circuit and effectively reduce the photoelectric signal conversion time, and it can also make it more lightweight and improve space utilization efficiency, and achieve higher computing power.

A nanosheet 1T-4R mask programed multi-level read-only memory component includes a plurality of nanosheet channels between a first source/drain and a second source/drain and a gate around the plurality of nanosheet channels. The component includes a first resistor upon a frontside surface of the first source/drain, a second resistor upon a frontside surface of the second source/drain, a third resistor upon a backside surface of the first source/drain, and a fourth resistor upon a backside surface of the second source/drain. Respective frontside contacts electrically connect the first resistor, the second resistor, and the gate to a frontside backend of line (BEOL) network. Respective backside contacts electrically connect the third resistor and the fourth resistor to a backside power delivery network (BSPDN).

A 3D device including: a first level including first transistors, a first interconnect; a second level including second transistors, the second level overlaying the first level and bonded to each other includes metal to metal bonding regions; at least four functional units each includes a first circuit which includes a portion of the first transistors; a redundancy circuit, where each of the at least four functional units includes a second circuit which includes a portion of the second transistors, and includes at least one memory control circuit and at least one memory array; where each of the at least four functional units includes a vertical connectivity structure which includes a plurality of pillars which provides electrical control connection between the first circuit and the second circuit; and a third transistor and a fourth transistor electrically connected to each other and are at least 100 mm apart.