A panel testing unit is provided, an array substrate including the panel testing unit and a liquid crystal display device including the array substrate. The panel testing unit includes at least a shorting bar set, each shorting bar set including at least a shorting line; at least a signal line set, each signal line set including at least a signal line. Any one of the signal lines is connected to a corresponding one of the shorting lines through a diode. A novel technical scheme is provided, a unidirectional diode is disposed between the signal line and the shorting line (test line), after the test is finished, a laser cutting process is not necessary, a processing of a next step can be performed directly, thus the processing cost is reduced, and the productivity is increased.

A two-terminal ferroelectric perovskite diode comprises a region of ferroelectric perovskite material positioned adjacent to a region of n-type doped perovskite semiconductor material. Asserting a positive voltage across the diode can cause the polarization of the ferroelectric perovskite material to be set in a first direction that causes the diode to be placed in a low resistance state due to the formation of an accumulation region in the perovskite semiconductor material at the ferroelectric perovskite-perovskite semiconductor boundary. Asserting a negative voltage across the diode can cause the polarization of the ferroelectric perovskite material to be set in a second direction that causes the diode to be placed in a high resistance state due to the formation of a depletion region in the perovskite semiconductor material at the ferroelectric perovskite-perovskite semiconductor material. These non-volatile low and high resistance states enable the diode to be used as a non-volatile memory element.

A design of a non-transistor memory core with corresponding shift register control logic may be all comprised of tunnel diodes and capacitors, and a method for fabricating such memories and control logic may use a stencil and non-lithographic self-aligning semiconductor processing steps to minimize cost. Designs and fabrication processes for I/O pads connected to the memory core and control logic are also presented.

A semiconductor device includes a semiconductor substrate, an internal circuit provided on the semiconductor substrate, a first and a second pads connected to the internal circuit, a first ESD protection circuit connectable to the first pad, and a second ESD protection circuit connectable to the second pad. The first ESD protection circuit includes a first ESD protection element, and the second ESD protection circuit includes a second and a third ESD protection elements. The second pad is connected to the internal circuit via the second ESD protection element, and the first pad is directly connected to the internal circuit.

A semiconductor device, and a method of manufacturing the semiconductor device, includes a transistor including a gate insulating layer and a gate electrode stacked on a substrate. The semiconductor device also includes a diode including a diode electrode, wherein the diode electrode is on the substrate, extends from the gate electrode, and is electrically connected to the gate electrode. The semiconductor device further includes a first plug physically and electrically connected to the diode electrode.

A method of preparing a programmable diode, including: forming a tungsten plug by a standard CMOS process; taking the tungsten plug as a lower electrode and depositing a functional layer material such as a ferroelectric film on the tungsten plug; depositing an upper electrode on the functional layer material; and patterning the upper electrode and a functional layer to complete a preparation of the programmable diode. The present disclosure further discloses a ferroelectric memory of a programmable diode prepared by the method of preparing a programmable diode. The method of preparing a programmable diode does not require growing a lower electrode and reduces a complexity of the process. The ferroelectric memory includes a transistor and a programmable diode. This design stores information according to different polarities of the diode, thus a device area may be further reduced and a storage density may be improved.

The present disclosure provides a high-density three-dimensional multilayer memory and a preparation method. The preparation method of the memory comprises the following steps: firstly forming a basic structure body; secondly, slotting the basic structure body; thirdly, forming a preset number of memory cell holes in the a segmentation groove, an insulating medium being arranged between every two adjacent memory cell holes, a vertical electrode being arranged in the memory cell hole, and a memory medium layer being arranged between the vertical electrode and an interdigital structure; and in the third step, before the memory medium is arranged, the preparation method comprises the following steps: performing doping diffusion on the first conducting medium located on the inner wall of the segmentation groove, so that the first conducting medium close to the inner wall of the segmentation groove forms a buffer area made of a low-doped semiconductor material.

Disclosed is a stateful logic-in-memory using silicon diodes. More particularly, the stateful logic-in-memory according to an embodiment of the present invention includes a plurality of silicon diodes, each of the silicon diodes includes an anode region, a first channel region, a second channel region and a cathode region and is included as a memory cell.

Provided are a semiconductor device and a method of fabricating the same.

The semiconductor device includes a semiconductor substrate, a first and a second diffusion region formed under a surface of the semiconductor substrate, a gate and a sidewall spacer stacked on the semiconductor substrate, wherein the first diffusion region is at least one active region not being intersected by the gate and the sidewall spacer, wherein the second diffusion region includes a part of an active region intersecting the gate and the sidewall spacer, wherein there is no gate insulating layer between the gate and the semiconductor substrate.

A memory device includes a well formed in a substrate and extending along a first lateral direction, wherein the well has a first conductive type. The memory device includes a plurality of epitaxial structures disposed over the well, wherein the plurality of epitaxial structures have a second conductive type opposite to the first conductive type. The memory device includes a common epitaxial structure disposed over the well, wherein the common epitaxial structure has the first conductive type and is in contact the well. A first group of the plurality of epitaxial structures are each in contact with the well, and a second group of the plurality of epitaxial structures each have a bottom surface separated from the well with a corresponding dielectric layer.