To provide a semiconductor device with excellent charge retention characteristics, an OS transistor is used as a transistor whose gate is connected to a node for retaining charge. Charge is stored in a first capacitor, and data at the node for retaining charge is read based on whether the stored charge is transferred to a second capacitor. Since a Si transistor, in which leakage current through a gate insulating film occurs, is not used as a transistor connected to the node for retaining charge, charge retention characteristics of the node are improved. In addition, the semiconductor device operates in data reading without requiring transistor performance equivalent to that of a Si transistor.

Example embodiments relate to a method of fabricating a synapse memory device capable of being driven at a low voltage and realizing a multi-level memory. The synapse memory device includes a two-transistor structure in which a drain region of a first transistor including a memory layer and a first source region of a second transistor share a source-drain shared area. The synapse memory device is controlled by applying a voltage through the source-drain shared area. The memory layer includes a charge trap layer and a threshold switching layer, and may realize a non-volatile multi-level memory function.

A method of forming a split gate memory cell structure using a substrate includes forming a gate stack comprising a select gate and a dielectric portion overlying the select gate. A charge storage layer is formed over the substrate including over the gate stack. A first sidewall spacer of conductive material is formed along a first sidewall of the gate stack extending past a top of the select gate. A second sidewall spacer of dielectric material is formed along the first sidewall on the first sidewall spacer. A portion of the first sidewall spacer is silicided using the second sidewall spacer as a mask whereby silicide does not extend to the charge storage layer.

A semiconductor device includes a 2-input NAND decoder and an inverter that have six MOS transistors arranged in a line. The MOS transistors of the decoder are formed in a planar silicon layer disposed on a substrate and each have a structure in which a drain, a gate, and a source are arranged vertically and the gate surrounds a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicon layer on a surface of the planar silicon layer.

Provided is a capacitor structure for a three-dimensional AND flash memory device. The capacitor includes a substrate having a capacitor array region and a capacitor staircase region, a circuit under array (CuA) structure disposed on the substrate, a bottom conductive layer disposed on the CuA structure, a stacked structure disposed on the bottom conductive layer, and pillar structures. The stacked structure includes dielectric layers and conductive layers alternately stacked. The conductive layers in the capacitor staircase region are arranged in a staircase form. The pillar structures are arranged in an array in the capacitor array region and penetrate through the stacked structure and the bottom conductive layer. A part of the conductive layers is 10 electrically connected to a first common voltage source, and the rest of the conductive layers and the bottom conductive layer are electrically connected to a second common voltage source.

The present disclosure provides a complementary phototransistor pixel unit, a sensing and computing array structure and an operation method thereof. The complementary phototransistor pixel unit includes: a first photoelectric field effect transistor, which is a photoelectric field effect transistor based on an ultra-thin body and buried oxide layer; and a second photoelectric field effect transistor, the second photoelectric field effect transistor is a photoelectric field effect transistor based on an ultra-thin body and buried oxide layer, each of the first photoelectric field effect transistor and the second photoelectric field effect transistor is four-end device and has a gate electrode G, a source electrode S, a drain electrode D, and a well base electrode B, and the source electrode S or drain electrode D of the first photoelectric field effect transistor is connected to the source electrode S or drain electrode D of the second photoelectric field effect transistor.

This application provides a method for fabricating an MOS capacitor based on a SONOS process, including: forming a gate oxide layer on the semiconductor structure, the gate oxide layer covering a SONOS unit region, an MOS capacitor region and other device regions; removing the gate oxide layer on the SONOS unit region and the MOS capacitor region; forming an ONO film layer on the SONOS unit region, the MOS capacitor region, and the gate oxide layer on the other device regions; and performing etching to remove the ONO film layer on the other device regions, and reserve the ONO film layer on the SONOS unit region and the MOS capacitor region. According to this application, the threshold voltage of the MOS capacitor itself is increased and the working voltage of the capacitor in the accumulation region is decreased, thus greatly improving the voltage withstand performance of the MOS capacitor.

A semiconductor device includes a major element including a first semiconductor region, a first electrode, a second electrode, a first gate electrode, and a first insulating member being positioned between the first gate electrode and the first semiconductor region, and a recording element electrically connected with the first electrode. The recording element records, as analog data, a maximum value of a change amount dV/dt of a voltage of the first electrode over time.

A method for making a memory device may include forming an array of memory cells on a semiconductor substrate. Each memory cell may include a first well on the semiconductor substrate having a first conductivity type, a second well adjacent the first well and having a second conductivity type and defining a depletion layer with the first well, and a superlattice within the depletion layer. The superlattice may include stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions, and trap source atoms within the stacked groups of layers. Each memory call may also include spaced apart source and drain regions adjacent the second well and defining a channel therebetween, and a gate overlying the channel.

A memory device may include an array of memory cells on a semiconductor substrate. Each memory cell may include a first well on the semiconductor substrate having a first conductivity type, a second well adjacent the first well and having a second conductivity type and defining a depletion layer with the first well, and a superlattice within the depletion layer. The superlattice may include stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. Trap source atoms may also be within the stacked groups of layers. Each memory cell may further include spaced apart source and drain regions adjacent the second well and defining a channel therebetween, and a gate overlying the channel.