An integrated circuit includes a first time delay circuit, a second time delay circuit, and a master-slave flip-flop having a gated input circuit and a transmission gate. The transmission gate is configured to receive the first clock signal and the second clock signal to control a transmission state of the transmission gate. The gated input circuit is configured to have an input transmission state controlled by the third clock signal at the second output of the second time delay circuit. The second time delay circuit further includes a second gate-conductor and a second gate via-connector in direct contact with the second gate-conductor. The second gate-conductor intersects a first-type active region structure and a second-type active region structure in a second area, and wherein at least a portion of the second gate via-connector is atop the second-type active region structure.

Embodiments provide a semiconductor structure. The semiconductor structure includes a substrate, a dielectric layer arranged on the substrate, and a plurality of memory cell layers. The plurality of memory cell layers are spaced in the dielectric layer along a first direction, and projections of any adjacent two of the plurality of memory cell layers on the substrate are overlapped. Each of the plurality of memory cell layers includes a plurality of memory cells spaced along a second direction. According to the embodiments, the plurality of memory cell layers are spaced in the dielectric layer along a direction perpendicular to the substrate, and each of the plurality of memory cell layers has a plurality of memory cells therein; and a source, a channel and a drain in each of the plurality of memory cells are arranged along a direction parallel to the substrate.

A semiconductor device includes a substrate; and a plurality of sub-word line drivers, each of the sub-word line drivers including a plurality of transistors, wherein at least one of the plurality of transistors has a buried gate structure positioned in the substrate.

A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate. The first and second fin structures have respective first and second vertical dimensions that are about equal to each other. The method further includes modifying the first fin structure such that the first vertical dimension of the first fin structure is smaller than the second vertical dimension of the second fin structure and depositing a dielectric layer on the modified first fin structure and the second fin structure. The method further includes forming a polysilicon structure on the dielectric layer and selectively forming a spacer on a sidewall of the polysilicon structure.

A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate. The first and second fin structures have respective first and second vertical dimensions that are about equal to each other. The method further includes modifying the first fin structure such that the first vertical dimension of the first fin structure is smaller than the second vertical dimension of the second fin structure and depositing a dielectric layer on the modified first fin structure and the second fin structure. The method further includes forming a polysilicon structure on the dielectric layer and selectively forming a spacer on a sidewall of the polysilicon structure.

A method of manufacturing a 3D device including: forming a first level including first transistors and a first interconnect; forming a second level including second transistors; overlaying the second level on the first level; and bonding the second level to the first level; the bonding includes performing metal region to metal region bonding, the 3D device includes at least four electronic circuits (AL4ECs) and at least one redundancy circuit, where the AL4ECs each include a first circuit which includes a portion of the first transistors, where the AL4ECs include a second circuit which includes a portion of the second transistors, where the AL4ECs each include a vertical connectivity structure (VCSt), the VCSt includes pillars, where the pillars are configured to provide electrical connections between the first circuit and the second circuit, and where the AL4ECs each include at least one memory control circuit and at least one memory array.

An integrated circuit includes a first time delay circuit, a second time delay circuit, and a flip-flop having a gated input circuit and a transmission gate. The first time delay circuit is configured to receive a first clock signal and to output a second clock signal. The second time delay circuit is configured to receive the second clock signal and to output a third clock signal. The transmission gate is controlled with the first clock signal and the second clock signal. The gated input circuit is controlled by the third clock signal. The first time delay circuit includes a first gate via-connector in direct contact with a first gate-conductor which intersects a first-type active region structure in a first area. The second time delay circuit includes a second gate via-connector in direct contact with a second gate-conductor which intersects a second-type active region structure in a second area.

The present disclosure relates to semiconductor structures and, more particularly, to memory devices and methods of manufacture. The structure includes: a gate structure having a gate dielectric material and a gate body; a body region under the gate dielectric material; a first doped region laterally adjacent to a first side of the body region; a second doped region laterally adjacent to the first doped region; and a shallow trench isolation structure laterally adjacent to a second side of the body region.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a valley inwardly positioned on a top surface of the substrate; a programmable insulating layer conformally positioned on the valley and including a V-shaped cross-sectional profile; and a top electrode positioned on the programmable insulating layer. The programmable insulating layer is configured to be blown out under a programming voltage.

A 3D device including: a first level including first transistors, a first interconnect; a second level including second transistors, the second level overlaying the first level and bonded to each other includes metal to metal bonding regions; at least four functional units each includes a first circuit which includes a portion of the first transistors; a redundancy circuit, where each of the at least four functional units includes a second circuit which includes a portion of the second transistors, and includes at least one memory control circuit and at least one memory array; where each of the at least four functional units includes a vertical connectivity structure which includes a plurality of pillars which provides electrical control connection between the first circuit and the second circuit; and a third transistor and a fourth transistor electrically connected to each other and are at least 100 mm apart.