A semiconductor apparatus includes a plurality of semiconductor devices. The semiconductor devices each include a ferroelectric layer, a conductive metal oxide layer, and a semiconductor layer, between two electrodes. The conductive metal oxide layer may be between the ferroelectric layer and the semiconductor layer. The ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer may all include a metal oxide. The conductive metal oxide layer may include one or more materials selected from the group consisting of an indium oxide, a zinc oxide, a tin oxide, and any combination thereof.

An electronic switching device, in particular tunnel junctions, containing an organic molecular layer for use in memory, sensors, field-effect transistors or Josephson junctions. More particularly, related to the field of random access non-volatile memristive memories (RRAM). Another aspect is a compound of formula I

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for use in a molecular layer. Also, the use of the molecular layer and processes for the production and operation of an electronic switching element and components based thereon.

An electronic switching device, in particular tunnel junctions, containing an organic molecular layer for use in memory, sensors, field-effect transistors or Josephson junctions. More particularly, related to the field of random access non-volatile memristive memories (RRAM). Another aspect is a compound of formula I

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for use in a molecular layer. Also, the use of the molecular layer and processes for the production and operation of an electronic switching element and components based thereon.

Programmable memory devices having a cross-point array of polymer junctions with individually-programmed conductances are provided. In one aspect, a method of forming a memory device includes: forming first metal lines on an insulating substrate; forming polymeric resistance elements on the first metal lines; and forming second metal lines over the polymeric resistance elements with a single one of the polymeric resistance elements present at each intersection of the first/second metal lines forming a cross-point array. A memory device and a method of operating a memory device are also provided.

A nanostructured cross-wire memory architecture is provided that can interface with conventional semiconductor technologies and be electrically accessed and read. The architecture links lower and upper sets of generally parallel nanowires oriented crosswise, with a memory element that has a characteristic conductance. Each nanowire end is attached to an electrode. Conductance of the linkages in the gap between the wires encodes the information. The nanowires may be highly-conductive, self-assembled, nucleic acid-based nanowires enhanced with dopants including metal ions, carbon, metal nanoparticles and intercalators. Conductance of the memory elements can be controlled by sequence, length, conformation, doping, and number of pathways between nanowires. A diode can also be connected in series with each of the memory elements. Linkers may also be redox or electroactive switching molecules or nanoparticles where the charge state changes the resistance of the memory element.

Disclosed are a memristor device, a method of fabricating the same, a synaptic device including a memristor device, and a neuromorphic device including a synaptic device. The disclosed memristor device may comprise a first electrode, a second electrode disposed to be spaced apart from the first electrode; and a resistance changing layer including a copolymer between the first electrode and the second electrode. The copolymer may be a copolymer of a first monomer and a second monomer, and the first polymer formed from the first monomer may have a property that diffusion of metal ions is faster than that of the second polymer formed from the second monomer. The second polymer may have a lower diffusivity of metal ions as compared with the first polymer. The first monomer may include vinylimidazole (VI). The second monomer may include 1,3,5-trivinyl-1,3,5-trimethylcyclotrisiloxane (V3D3). The copolymer may include p(V3D3-co-VI).

Disclosed are a memristor device, a method of fabricating the same, a synaptic device including a memristor device, and a neuromorphic device including a synaptic device. The disclosed memristor device may comprise a first electrode, a second electrode disposed to be spaced apart from the first electrode; and a resistance changing layer including a copolymer between the first electrode and the second electrode. The copolymer may be a copolymer of a first monomer and a second monomer, and the first polymer formed from the first monomer may have a property that diffusion of metal ions is faster than that of the second polymer formed from the second monomer. The second polymer may have a lower diffusivity of metal ions as compared with the first polymer. The first monomer may include vinylimidazole (VI). The second monomer may include 1,3,5-trivinyl-1,3,5-trimethylcyclotrisiloxane (V3D3). The copolymer may include p(V3D3-co-VI).

A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part. The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.

The present disclosure generally relates to multi-switch storage cells (MSSCs), three-dimensional MSSC arrays, and three-dimensional MSSC memory. Multi-switch storage cells include a cell select device, multiple resistive change elements, and an intracell wiring electrically connecting the multiple resistive change elements together and to the cell select device. MSSC arrays are designed (architected) and operated to prevent inter-cell (sneak path) currents between multi-switch storage cells, which prevents stored data disturb from adjacent cells and adjacent cell data pattern sensitivity. Additionally, READ and WRITE operations may be performed on one of the multiple resistive change elements in a multi-switch storage cell without disturbing the stored data in the remaining resistive change elements. However, controlled parasitic currents may flow in the remaining resistive change elements within the cell. Isolating each multi-switch storage cell in a three-dimensional MSSC array, enables in-memory computing for applications such as data processing for machine learning and artificial intelligence.

The present disclosure generally relates to multi-switch storage cells (MSSCs), three-dimensional MSSC arrays, and three-dimensional MSSC memory. Multi-switch storage cells include a cell select device, multiple resistive change elements, and an intracell wiring electrically connecting the multiple resistive change elements together and to the cell select device. MSSC arrays are designed (architected) and operated to prevent inter-cell (sneak path) currents between multi-switch storage cells, which prevents stored data disturb from adjacent cells and adjacent cell data pattern sensitivity. Additionally, READ and WRITE operations may be performed on one of the multiple resistive change elements in a multi-switch storage cell without disturbing the stored data in the remaining resistive change elements. However, controlled parasitic currents may flow in the remaining resistive change elements within the cell. Isolating each multi-switch storage cell in a three-dimensional MSSC array, enables in-memory computing for applications such as data processing for machine learning and artificial intelligence.