The current disclosure describes techniques for forming semiconductor structures having multiple semiconductor strips configured as channel portions. In the semiconductor structures, diffusion break structures are formed after the gate structures are formed so that the structural integrity of the semiconductor strips adjacent to the diffusion break structures will not be compromised by a subsequent gate formation process. The diffusion break extends downward from an upper surface until all the semiconductor strips of the adjacent channel portions are truncated by the diffusion break.

A flexible sensor includes a substrate having flexibility; and a sensor element provided on the substrate, wherein the sensor element includes a transistor having a gate electrode, a source electrode, and a drain electrode; and a variable resistance portion connected to either of the gate electrode, the source electrode, and the drain electrode, and the variable resistance portion has a resistance value changeable due to a strain, and wherein the variable resistance portion includes an extension portion extending in a direction.

In example implementations, an organic light emitting transistor is provided. The organic light emitting transistor includes a substrate, at least one layer deposited onto the substrate, a thin film transistor, and an organic light emitting transistor. The thin film transistor is formed on the substrate to include a first portion of the at least one layer and the organic light emitting transistor is formed on the substrate to include a second portion of the at least one layer.

A thin film transistor, a manufacturing method of the same, and a CMOS inverter are provided. The thin film transistor includes a base substrate, a dielectric layer, and a semiconductor layer. A first channel is provided between the source and the drain. Carbon nanotubes are provided in the first channel. A second channel is provided between the drain and the gate. An ion gel is provided in the second channel. By regulating a composition of the ion gel and a content of a dopant, a threshold voltage of a carbon nanotube thin film transistor is effectively controlled.

Embodiments of the present disclosure provide a metadevice including a substrate, a resonator loop coupled to the substrate. The resonator loop having a first gap in the resonator loop. The metadevice includes an organic electrochemical transistor positioned in the first gap, a gate electrode, and an electrolyte extending between the organic electrochemical transistor and the gate electrode.

Provided are a display panel, a preparation method thereof, and a display apparatus. The display panel includes an array substrate and a color filter substrate aligned and combined into a cell. The color filter substrate includes a first base substrate and a plurality of color resist blocks arranged at intervals on the first base substrate. The array substrate includes a second base substrate and a plurality of pixel electrodes arranged at intervals on the second base substrate. The pixel electrodes are in one-to-one correspondence with the color resist blocks. The display panel includes a bending area and a non-bending area located at least on one side of the bending area. A density of the pixel electrodes in the bending area is less than that in the non-bending area, and a density of the color resist blocks in the bending area is less than that in the non-bending area.

A technology called RINSE (Removal of Incubated Nanotubes through Selective Exfoliation) is demonstrated. RINSE removes carbon nanotube (CNT) aggregates in CNFETs without compromising CNFET performance. In RINSE, CNTs are deposited on a substrate, coated with a thin adhesive layer, and sonicated. The adhesive layer is strong enough to keep the individual CNTs on the substrate, but not the larger CNT aggregates. When combined with a CNFET CMOS process as disclosed here, record CNFET CMOS yield and uniformity can be realized.

A carbon nanotube field effect transistor (CNFET), that has a channel formed of carbon nanotubes (CNTs), includes a layered deposit of a nonstoichiometric doping oxide (NDO), such as HfO.sub.X, where the concentration of the NDO varies through the thickness of the layer(s). An n-type metal-oxide semiconductor (NMOS) CNFET made in this manner can achieve similar ON-current, OFF-current, and/or threshold voltage magnitudes to a corresponding p-type metal-oxide semiconductor (PMOS) CNFET. Such an NMOS and PMOS can be used to achieve a symmetric complementary metal-oxide semiconductor (CMOS) CNFET design.

A technique comprising: producing an unencapsulated stack of layers defining one or more electronic devices including an organic semiconductor element; and then subjecting the unencapsulated stack of layers to a water removal treatment in a vacuum oven in the presence of an external water adsorbent; wherein the water removal treatment comprises heating the unencapsulated stack of layers in the vacuum oven for a time period longer than a control time period at which a spike in oven pressure attributable to the release of water from the stack of layers would occur with heating under the same treatment conditions but without the water absorbing material.

Disclosed are a thin film transistor including a source electrode and a drain electrode facing each other, a channel region between the source electrode and the drain electrode, and a gate electrode overlapped with the channel region, wherein the channel region includes a plurality of semiconductor stripes extending in a direction from the source electrode to the drain electrode, a method of manufacturing the same, a thin film transistor array panel, and an electronic device.