Disclosed are a thin film transistor including a source electrode and a drain electrode facing each other, a channel region between the source electrode and the drain electrode, and a gate electrode overlapped with the channel region, wherein the channel region includes a plurality of semiconductor stripes extending in a direction from the source electrode to the drain electrode, a method of manufacturing the same, a thin film transistor array panel, and an electronic device.

The present invention relates to an organic thin film transistor (OTFT) comprising an organic semiconductor layer (2) arranged between a source terminal (3) and a drain terminal (4). The OTFT further includes a front gate (5) electrode arranged on one side of the organic semiconductor layer and a back gate electrode (6) arranged on the opposite side of the organic semiconductor layer. The front and back gate electrodes are arranged to control the current flow in the organic semiconductor layer upon application of a voltage and the back gate electrode is electrically connected to one of: the front gate electrode and the source terminal. OTFT's according to the present invention, with a connection between the back gate and the source or front gate, exhibit improved turn on voltage stability, lower power consumption and improved bias stress stability compared to single gate and back gate isolated OTFTs.

The present invention relates to an organic thin film transistor (OTFT) comprising an organic semiconductor layer (2) arranged between a source terminal (3) and a drain terminal (4). The OTFT further includes a front gate (5) electrode arranged on one side of the organic semiconductor layer and a back gate electrode (6) arranged on the opposite side of the organic semiconductor layer. The front and back gate electrodes are arranged to control the current flow in the organic semiconductor layer upon application of a voltage and the back gate electrode is electrically connected to one of: the front gate electrode and the source terminal. OTFT's according to the present invention, with a connection between the back gate and the source or front gate, exhibit improved turn on voltage stability, lower power consumption and improved bias stress stability compared to single gate and back gate isolated OTFTs.

In an embodiment, the present disclosure pertains to a packaging label (1) comprising a substrate (10), a display (6) placed above the substrate (10), a control module (4) placed in electrical contact with the display (6) and adapted to control the operation of said display (6), at least one photovoltaic module (2) placed above the substrate (10) and next to the display (6) and predisposed to supply the display (6) and the control module (4); wherein the photovoltaic module (2), the control module (4) and the display (6) are printed on the substrate (10) using a printing ink mixed with dopants.

A device including a stack of layers defining a first conductor pattern at a first level of the stack and one or more semiconductor channels in respective regions, connecting a pair of parts of the first conductor pattern, and capacitively coupled via a dielectric to a coupling conductor of a second conductor pattern at a second level of the stack. The stack includes at least two insulator patterns over which the first level or second level conductor patterns is formed. A first insulator pattern occupies one or more semiconductor channel regions to provide the dielectric. The second insulator pattern defines one or more windows in the one or more semiconductor channel regions through which the second conductor pattern contacts the first insulator pattern other than via the second insulator pattern. The second insulator pattern overlaps the first insulator pattern outside the one or more semiconductor channel regions.

Carbon allotropes, a thin-film transistor array substrate comprising the same, and a display device comprising the same are disclosed. The thin-film transistor array substrate comprising a substrate, a gate electrode on the substrate, a gate insulating film on the gate electrode, an active layer positioned on the gate insulating film and comprising a semiconductor material and a plurality of carbon allotropes, and a source electrode and a drain electrode that make contact with the active layer.

A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.

A thin film transistor array including thin film transistor elements including an insulating substrate, a gate electrode, a gate insulating film, a source electrode, a drain electrode, and a channel region formed between the source electrode and the drain electrode, the thin film transistor elements being arrayed in a matrix, a disconnection pattern including an insulating material and formed in stripes extending over the thin film transistor elements, the disconnection pattern having a maximum film thickness of 200 nm-3000 nm, and a semiconductor pattern formed in stripes perpendicular to the disconnection pattern and extending over the channel region of the thin film transistor elements, the semiconductor pattern being disconnected at an intersection with the disconnection pattern.

In a method of forming a gate-all-around field effect transistor (GAA FET), a bottom support layer is formed over a substrate and a first group of carbon nanotubes (CNTs) are disposed over the bottom support layer. A first support layer is formed over the first group of CNTs and the bottom support layer such that the first group of CNTs are embedded in the first support layer. A second group of carbon nanotubes (CNTs) are disposed over the first support layer. A second support layer is formed over the second group of CNTs and the first support layer such that the second group of CNTs are embedded in the second support layer. A fin structure is formed by patterning at least the first support layer and the second support layer.

A transistor comprises a channel region between a source region and a drain region, a dielectric material adjacent to the channel region, an electrode adjacent to the dielectric material, and an electrolyte between the dielectric material and the electrode. Related semiconductor devices comprising at least one transistors, related electronic systems, and related methods are also disclosed.