A technique comprising: forming a first conductor pattern at least partly defining source and/or drain conductors for one or more thin film transistor devices; exposing the conductor pattern to a reactive halogen species; and depositing organic semiconductor channel material directly over the exposed first conductor pattern to provide one or more semiconductor channels between source and drain conductors of the exposed first conductor pattern.

A method and system utilizes ink jetting or printing of surface work function modification material or solution to form modified p-type and/or n-type electrodes. The proposed method is suitable for making complementary OTFT circuits in roll-to-roll fabrication environment.

The present application provides a method for fabricating a thin film transistor, a method for fabricating an array substrate, and a display apparatus. A method for fabricating a thin film transistor including: providing a substrate; covering an isolating layer on the substrate; coating an active layer precursor solution on the isolation layer; forming an active layer thin film by the active layer precursor solution; dividing the active layer thin film into a small module active layer, the mobility of the active layer of the thin film transistor is increased, and to drive the quantum dot light emitting device of the array substrate through the thin film transistor with high mobility to improve the display luminescence performance of the display apparatus.

A technique comprising: forming a conductor layer in contact with a dielectric layer; patterning the conductor layer using an acidic patterning agent to form a source-drain conductor pattern for one or more transistors at a surface of a workpiece; and forming an organic semiconductor layer over the surface of the workpiece to provide one or more semiconductor channels for the one or more transistors; wherein the method further comprises: prior to forming the conductor layer, treating the dielectric layer with an alkaline agent.

A memory array includes: a plurality of first wires; at least one second wire crossing the first wires; and a plurality of memory elements provided in correspondence with respective intersections of the first wires and the at least one second wire and each having a first electrode and a second electrode arranged spaced apart from each other, a third electrode connected to one of the at least one second wire, and an insulating layer that electrically insulates the first electrode and the second electrode and the third electrode from each other, the first wires, the at least one second wire, and the first wires, the at least one second wire, and the memory elements being formed on a substrate.

An electronic component such as a voltage controllable reconfigurable capacitor or transistor is formed by printing one or more layers of ink on a non-conductive substrate. Ferroelectric ink or semi-conductive ink is printed and conductive resistive or dielectric ink is printed on a s same or different layers. Reconfigurability is achieved by printing resistive biasing circuitry wherein when a changing voltage is applied to the biasing circuitry, an electronic property of the electronic component changes in response to the changing voltage.

A technique, comprising: forming, over a substrate (2) comprising at least source and drain conductors (4, 6) for one or more transistor devices, at least a first, semiconductor layer (8) providing one or more semiconductor channels for the one or more transistor devices; forming, over the first layer, a second layer (10) that defines at least part of a gate dielectric for the one or more transistor devices; creating a pattern in the second layer, without depositing any temporary material onto the second layer; and using the pattern in the second layer to pattern the first layer.

A method for making a metal oxide semiconductor carbon nanotube thin film transistor circuit. A p-type carbon nanotube thin film transistor and a n-type carbon nanotube thin film transistor are formed on an insulating substrate and stacked with each other. The p-type carbon nanotube thin film transistor includes a first semiconductor carbon nanotube layer, a first drain electrode, a first source electrode, a functional dielectric layer, and a first gate electrode. The n-type carbon nanotube thin film transistor includes a second semiconductor carbon nanotube layer, a second drain electrode, a second source electrode, a first insulating layer, and a second gate electrode. The first drain electrode and the second drain electrode are electrically connected with each other. The first gate electrode and the second gate electrode are electrically connected with each other.

According to one embodiment, a method includes forming, at a low temperature, a thin film transistor structure above a flexible substrate in a film thickness direction. The low temperature is less than about 200 C., and the thin film transistor structure includes a contact pad on a lower or upper surface thereof. The method also includes forming, at a high temperature, a perpendicular magnetic tunnel junction (pMTJ) structure above a rigid substrate. The high temperature is greater than about 200 C. The method also includes removing the rigid substrate from below the pMTJ structure and bonding, at the low temperature, the pMTJ structure to the thin film transistor structure using an adhesion layer. Other methods of forming flexible substrates for mounting pMTJs and systems thereof are described in accordance with more embodiments.

Provided is an apparatus for generating a digital value, including: an identification value generator including a plurality of unit cells; and an identification value extractor outputting an identification value of a plurality of bits by using output values of the plurality of unit cells, wherein each of the plurality of unit cells includes an identification value generating element including a first upper electrode and a second upper electrode formed on the same layer, and determines the output value according to electrical connection or cut-off of the first upper electrode and the second upper electrode.