A sensor sheet includes unit sensor sheets configured to detect a physical property value at multiple points on a sensor layer, each unit sensor sheet including a first substrate, and an electrode layer and the sensor layer sequentially formed on one side of the first substrate; and a wiring substrate to which the unit sensor sheets are configured to be coupled, the wiring substrate including a second substrate, and a plurality of wirings provided on one side of the second substrate. One side of the wiring substrate and one side of each unit sensor sheet are facing each other. A conductive bonding member configured to electrically couple each unit sensor sheet and the wiring substrate with each other, is included between the electrode layer of each unit sensor sheet and at least one of the wirings of the wiring substrate.

A memory device according to an embodiment includes a fluid layer extending in a first direction, a particle in the fluid layer, a first control electrode made of a first material, a first insulating film provided between the fluid layer and the first control electrode, a second control electrode made of a second material and provided to be spaced apart from the first control electrode in the first direction, a second insulating film provided between the fluid layer and the second control electrode, a third control electrode made of a third material different from the first material and the second material and provided between the first control electrode and the second control electrode, and a third insulating film provided between the fluid layer and the third control electrode.

An integrated circuit includes a memory array that stores data, a rectifying circuit that rectifies an alternating current and generates a direct-current voltage, and a logic circuit that reads data stored in a memory. The memory array includes a first semiconductor memory element having a first semiconductor layer. The rectifying circuit includes a second semiconductor rectifying element having a second semiconductor layer. The logic circuit includes a third semiconductor logic element having a third semiconductor layer. The second semiconductor layer is a functional layer exhibiting a rectifying action and the third semiconductor layer is a channel layer of a logic element. All the first, second and third semiconductor layers, the functional layer exhibiting a rectifying action and the channel layer are formed of the same material including at least one selected from an organic semiconductor, a carbon nanotube, graphene, or fullerene.

A semiconductor device according to an embodiment of the present disclosure includes a substrate, a resistance change layer disposed on the substrate and including a plurality of carbon nanostructures, a channel layer disposed on the resistance change layer, a gate electrode layer disposed on the channel layer, and a source electrode layer and a drain electrode layer disposed to contact portions of the channel layer.

A display panel according to one embodiment of the present disclosure includes a substrate, an active electrode over the substrate and including a source region, a drain region, and a channel region, and an active upper electrode of a curved shape over the active electrode. The channel region of the active electrode and the active upper electrode may overlap each other and the channel region may have a same shape as the active upper electrode. Accordingly, a driving element included in the display panel may generate a high driving current and the degree of integration in a pixel may be improved.

In a method of forming a gate-all-around field effect transistor, a gate structure is formed surrounding a channel portion of a carbon nanotube. An inner spacer is formed surrounding a source/drain extension portion of the carbon nanotube, which extends outward from the channel portion of the carbon nanotube. The inner spacer includes two dielectric layers that form interface dipole. The interface dipole introduces doping to the source/drain extension portion of the carbon nanotube.

The current disclosure describes techniques for forming semiconductor structures having multiple semiconductor strips configured as channel portions. In the semiconductor structures, diffusion break structures are formed after the gate structures are formed so that the structural integrity of the semiconductor strips adjacent to the diffusion break structures will not be compromised by a subsequent gate formation process. The diffusion break extends downward from an upper surface until all the semiconductor strips of the adjacent channel portions are truncated by the diffusion break.

A thin film transistor array panel and a manufacturing method are disclosed herein. The thin film transistor array panel includes a data line, a first block of a source electrode, a third block of a drain electrode, and an electrode layer which are formed by a first metal layer disposed on a baseplate; a second block of the source electrode, a fourth block of the drain electrode are formed by a second metal layer which is disposed on the first metal layer. The first block and the second block overlap to combine integrally. The third block and the fourth block overlap to combine integrally. The present invention can decrease the electrical resistance of each of the source electrode and the drain electrode.

A method for the fabrication of organic electronic devices includes forming a fluoropolymer layer over a first area of a substrate and a first set of organic electronic devices. The first set of organic electronic devices are pre-fabricated on a second area of the substrate. The method further includes selectively removing the formed fluoropolymer layer from areas within the first area of the substrate by using a liquid solvent. The method further includes subsequent fabrication of organic electronic devices on the substrate.

A method of operating a device comprising: a first conductor layer defining a plurality of source conductors each associated with a respective group of transistors, and a plurality of drain conductors each associated with a respective transistor; a semiconductor layer defining semiconductor channels between said source and drain conductors; a second conductor layer defining a plurality of gate conductors each associated with a respective set of transistors, and one or more storage capacitor conductors capacitively coupled to the drain conductors for a respective set of transistors; the method comprising: using the gate conductors to switch the transistors between on and off states; and using the storage capacitor conductors to reduce the conductivity of one or more semiconductor layer connecting the drain conductor of each transistor in the on state to source and/or drain conductors other than those associated with that transistor.