Apparatus and associated methods related to a three dimensional integrated logic circuit that includes a columnar active region. Within the columnar active region resides an interdigitated plurality of semiconductor columns and conductive columns. A plurality of transistors is vertically arranged along each semiconductor column, which extends from a bottom surface of the columnar logic region to a top surface of the columnar logic region. The plurality of transistors are electrically interconnected so as to perform a logic function and to generate a logic output signal at a logic output port in response to a logic input signal received at a logic input port. Each of the plurality of conductive columns is adjacent to at least one of the plurality of semiconductor columns and extends along a columnar axis to one or more interconnection layers at the top and/or bottom surfaces of the columnar active layer.

In a method of forming a gate-all-around field effect transistor (GAA FET), a bottom support layer is formed over a substrate and a first group of carbon nanotubes (CNTs) are disposed over the bottom support layer. A first support layer is formed over the first group of CNTs and the bottom support layer such that the first group of CNTs are embedded in the first support layer. A second group of carbon nanotubes (CNTs) are disposed over the first support layer. A second support layer is formed over the second group of CNTs and the first support layer such that the second group of CNTs are embedded in the second support layer. A fin structure is formed by patterning at least the first support layer and the second support layer.

A method of fabricating an electrical circuit assembly on a flexible substrate comprises: identifying one or more bending-sensitive elements of an electrical circuit assembly, each bending-sensitive element having a performance that varies when said bending-sensitive element is flexed; splitting said one or more bending-sensitive elements into a first portion and a second portion, wherein the first portion and the second portion are functionally equivalent and together equate to said bending-sensitive element; printing the first portion of said bending-sensitive element on a first surface of the flexible substrate; printing the second portion of said bending-sensitive element on a second surface of the flexible substrate, diametrically opposite the first portion such that bending of the flexible substrate has an opposite effect on each of the first and second portions thereby serving to substantially cancel the effect on each portion out; and electrically connecting the first portion and the second portion.

An apparatus comprising: a module; a substrate; and electrolyte between the module and the substrate, wherein an electronic component is formed between the module and the substrate and wherein the electrolyte is configured to function as the electrolyte in the electronic component and also as the adhesive to attach the module to the substrate.

A transistor device comprising an inorganic oxide semiconductor channel having a channel length L and a channel width W between source and drain conductors and capacitively coupled to a gate conductor via an organic polymer dielectric in contact with the inorganic oxide semiconductor channel. The gate voltage required to maintain a constant current of at least X nA between the source and drain conductors over a period of 14 hours while the gate and drain conductors are maintained at the same electric potential, varies by less than 1V, preferably less than about 0.2V; wherein X equals the W/L ratio multiplied by 50.

An apparatus comprising: a plurality of sensors (501) arranged in an array (500), each sensor having a source electrode (504), a drain electrode (503), a gate electrode (505) and a channel, wherein the source electrode and drain electrode are elongate and the channel has a channel width defined by the longitudinal extent of the source and/or drain electrode and a channel length defined by the separation between the source and drain electrodes; a common conductive or semiconductive layer (506), which may be made of graphene, comprising the channels of the sensors (501) and arranged to extend over the plurality of sensors of the array and configured to be in electrical contact with at least the source electrode and the drain electrode of each sensor; and wherein the source electrode or drain electrode of each sensor forms a substantially continuous sensor perimeter at least along the channel width, which substantially encloses the other electrode of each sensor to inhibit the flow of charge carriers beyond the sensor perimeter to inhibit crosstalk between sensors in the array.

A method and system utilizes ink jetting or printing of surface work function modification material or solution to form modified p-type and/or n-type electrodes. The proposed method is suitable for making complementary OTFT circuits in roll-to-roll fabrication environment.

We describe a method for reducing a parasitic resistance at an interface between a conducting electrode region and an organic semiconductor in a thin film transistor, the method comprising: providing a solution comprising a dopant for doping said semiconductor, and depositing said solution onto said semiconductor and/or said conducting electrode region to selectively dope said semiconductor adjacent said interface between said conducting electrode region and said semiconductor, wherein depositing said solution comprises inkjet-printing said solution.

The present disclosure relates to an array substrate and a method for manufacturing the same. The array substrate includes a thin film transistor and comprises at least a first region and a second region. A thickness of an active layer of the thin film transistor in the first region is different from that of an active layer of the thin film transistor in the second region. A ratio of the overlapped area between the source electrode or the drain electrode and the active layer of the thin film transistor to the thickness of the active layer is kept uniform over the first region and the second region.

A problem addressed by the present invention is to provide a semiconductor device that is free from deterioration over time, is stable, and has n-type semiconductor characteristics. A main object of the present invention is to provide a semiconductor device that is characterized by including: a substrate; a source electrode, a drain electrode, and a gate electrode; a semiconductor layer in contact with the source electrode and the drain electrode; a gate insulating layer insulating the semiconductor layer from the gate electrode; and a second insulating layer in contact with the semiconductor layer on the opposite side of the semiconductor layer from the gate insulating layer; wherein the semiconductor layer contains a carbon nanotube; wherein the second insulating layer contains an electron-donating material having one or more selected from a nitrogen atom and a phosphorus atom; and wherein the second insulating layer has an oxygen permeability of 4.0 cc/(m.sup.2.Math.24 h.Math.atm) or less.