A device including a stack of layers defining a first conductor pattern at a first level of the stack and one or more semiconductor channels in respective regions, connecting a pair of parts of the first conductor pattern, and capacitively coupled via a dielectric to a coupling conductor of a second conductor pattern at a second level of the stack. The stack includes at least two insulator patterns over which the first level or second level conductor patterns is formed. A first insulator pattern occupies one or more semiconductor channel regions to provide the dielectric. The second insulator pattern defines one or more windows in the one or more semiconductor channel regions through which the second conductor pattern contacts the first insulator pattern other than via the second insulator pattern. The second insulator pattern overlaps the first insulator pattern outside the one or more semiconductor channel regions.

Various embodiments provide a method of forming an organic inverter including a first transistor and a second transistor. The method may include providing a substrate with a dielectric layer formed on top of the substrate; depositing a first semiconductor polymer layer on a first region of the dielectric layer; forming a first electrode and a second electrode on the first semiconductor polymer layer, thereby forming the first transistor located at the first region of the dielectric layer; forming a plurality of grooves on a surface of a second region of the dielectric layer; depositing a second semiconductor polymer layer on the second region of the dielectric layer; and forming a first electrode and a second electrode on the second semiconductor polymer layer, thereby forming the second transistor located at the second region of the dielectric layer.

In a method of forming a gate-all-around field effect transistor (GAA FET), a bottom support layer is formed over a substrate and a first group of carbon nanotubes (CNTs) are disposed over the bottom support layer. A first support layer is formed over the first group of CNTs and the bottom support layer such that the first group of CNTs are embedded in the first support layer. A second group of carbon nanotubes (CNTs) are disposed over the first support layer. A second support layer is formed over the second group of CNTs and the first support layer such that the second group of CNTs are embedded in the second support layer. A fin structure is formed by patterning at least the first support layer and the second support layer.

A field effect transistor (FET) structure includes a substrate, an internal gate, an insulation layer, a semiconductor strip, a gate dielectric insulator, and a gate conductor. The internal gate includes a floor portion located on the substrate and a wall portion extending from the floor portion. The insulation layer is located on the floor portion of the internal gate. The semiconductor strip is located on the wall portion and a portion of the insulation layer, and the semiconductor strip includes source/drain regions and a channel region adjacent to the source/drain regions. The gate dielectric insulator is located on the channel region. The gate conductor is located on the gate dielectric insulator.

An organic x-ray detector and a method of making the organic x-ray detector are disclosed. The x-ray detector includes a TFT array disposed on a substrate, an organic photodiode layer disposed on the TFT array, a barrier layer disposed on the photodiode layer, and a scintillator layer disposed on the barrier layer, such that the barrier layer includes at least one inorganic material.

A display apparatus includes: an emission layer including a light-emitting element which generates and emits light; a driving layer which drives the light-emitting element of the emission layer to generate and emit the light; and an adhesive layer which connects the light-emitting element to the driving layer. The driving layer includes: a substrate; and a conductive layer on the substrate and connected to the light-emitting element of the emission layer by the adhesive layer. The emission layer includes: a bank layer on the conductive layer of the driving layer, and an opening in the bank layer which exposes a portion of the conductive layer of the driving layer. The adhesive layer is disposed between the exposed portion of the conductive layer and the light-emitting element, and extends therefrom to be disposed on inner surfaces of the bank layer at the opening.

Disclosed is a CMOS element. The CMOS element comprises a substrate, a first metal layer, an insulation layer and a first type metal oxide semiconductor layer; and the element further comprises a first, a second and a third metal parts which are located on the insulation layer, and the first and the second metal parts are located at two sides of the first type metal oxide semiconductor layer and both contacts therewith; a second type organic semiconductor layer, located in a gap between the second, and the third metal parts and on the second, the third metal parts where are adjacent to the gap; a passivation layer, located on the first, the second and the third metal parts, the first type metal oxide semiconductor layer and the second type organic semiconductor layer; a third metal layer located on the passivation layer corresponding to the second type organic semiconductor layer.

A transistor comprises a channel region between a source region and a drain region, a dielectric material adjacent to the channel region, an electrode adjacent to the dielectric material, and an electrolyte between the dielectric material and the electrode. Related semiconductor devices comprising at least one transistors, related electronic systems, and related methods are also disclosed.

Oxacycloolefinic polymers as typically obtained by metathesis polymerization using Ru-catalysts, show good solubility and are well suitable as dielectric material in electronic devices such as capacitors and organic field effect transistors.

A thin film transistor includes a gate electrode, an insulation film disposed on the gate electrode, a semiconductor layer facing the gate electrode with the insulation film in between, and a source-drain wiring layer electrically coupled to the semiconductor layer, and including a first wiring layer and a second wiring layer. The first wiring layer is in contact with the semiconductor layer between the semiconductor layer and the insulation film, and is configured of a transparent electroconductive film. The second wiring layer is overlapped with a portion of the first wiring layer. Another semiconductor layer made of a material same as a material of the semiconductor layer is stacked on the second wiring layer.