A semiconductor device is disposed and includes a substrate, on which a scan line, a data line, a source electrode, a drain electrode, an organic semiconductor pattern, an organic insulating layer, a gate electrode, and an organic protection layer are disposed. The source electrode is electrically connected to the data line. The organic semiconductor pattern is disposed between the source electrode and the drain electrode. The organic insulating layer is disposed on an upper surface and a side surface of the organic semiconductor pattern. The organic insulating layer is at least disposed between the side surface of the organic semiconductor pattern and the gate electrode and disposed between the upper surface of the organic semiconductor pattern and the gate electrode. The gate electrode is electrically connected to the scan line. The organic protection layer covers the gate electrode.

Methods and devices for forming painted circuits using multiple layers of electrically conductive paint. In one aspect, a painted circuit includes a substrate (111) and one or more paint layer (106, 108, 110, 112, 114, 116, 120, 122) applied to the substrate, where the one or more paint layers each form an electrical component of the painted circuit. A given paint layer of the one or more paint layers includes a conductive paint formulation having a resistance that is defined by a concentration of conductive material that is included in the conductive paint formulation and a thickness of the given paint layer, and lower concentrations of the conductive material included in the conductive paint formulation provide a higher resistance than higher concentrations of conductive material.

An integrated circuit (IC) package product, e.g., system-on-chip (SoC) or system-in-package (SiP) product, may include at least one integrated inductor having a core magnetic field (B field) that extends parallel to the substrate major plane of at least one die or chiplet included in or mounted to the product, which may reduce the eddy currents within each die/chiplet substrate, and thereby reduce energy loss of the indictor. The IC package product may include a horizontally-extending IC package substrate, a horizontally-extending die mount base arranged on the IC package substrate, at least one die mounted to the die mount base in a vertical orientation, and an integrated inductor having a B field extending in a vertical direction parallel to the silicon substrate of each vertically-mounted die, thereby providing a reduced substrate loss in the integrated inductor, which provides an increased quality factor (Q) of the inductor.

An integrated circuit (IC) package product, e.g., system-on-chip (SoC) or system-in-package (SiP) product, may include at least one integrated inductor having a core magnetic field (B field) that extends parallel to the substrate major plane of at least one die or chiplet included in or mounted to the product, which may reduce the eddy currents within each die/chiplet substrate, and thereby reduce energy loss of the indictor. The IC package product may include a horizontally-extending IC package substrate, a horizontally-extending die mount base arranged on the IC package substrate, at least one die mounted to the die mount base in a vertical orientation, and an integrated inductor having a B field extending in a vertical direction parallel to the silicon substrate of each vertically-mounted die, thereby providing a reduced substrate loss in the integrated inductor, which provides an increased quality factor (Q) of the inductor.

Provided is a semiconductor device having a dual gate field-effect transistor and a sensor in electrical communication with the transistor. The field-effect transistor can have a first gate electrode, a second gate electrode, a source electrode, a drain electrode, a semiconductor layer with parts in contact with the source and drain electrodes, a bi-layer gate insulator, and a second gate insulator. The bi-layer gate insulator can include a first layer and a second layer, the first layer located between the second layer and a first side of the semiconductor layer, the second layer located between the first layer and the first gate electrode. The second gate insulator can be located between the second gate electrode and a second side of the semiconductor layer, and the sensor can be in electrical communication with the second gate electrode.

A biosensor for an analyte monitoring system. In one embodiment, the biosensor includes a cascode common source transimpedance amplifier circuit, an analog to digital converter, and an output circuit. The cascode common source transimpedance amplifier circuit is configured to receive an electrical current generated by an electrochemical reaction of an analyte on a test strip. The cascode common source transimpedance amplifier circuit is also configured to convert the electrical current to an analog voltage signal. The analog to digital converter is configured to convert the analog voltage signal to a digital voltage signal. The output circuit is configured to transmit a signal indicating a measured level of the analyte based on the digital voltage signal.

A biosensor for an analyte monitoring system. In one embodiment, the biosensor includes a cascode common source transimpedance amplifier circuit, an analog to digital converter, and an output circuit. The cascode common source transimpedance amplifier circuit is configured to receive an electrical current generated by an electrochemical reaction of an analyte on a test strip. The cascode common source transimpedance amplifier circuit is also configured to convert the electrical current to an analog voltage signal. The analog to digital converter is configured to convert the analog voltage signal to a digital voltage signal. The output circuit is configured to transmit a signal indicating a measured level of the analyte based on the digital voltage signal.

A thin film transistor, a manufacturing method of the same, and a CMOS inverter are provided. The thin film transistor includes a base substrate, a dielectric layer, and a semiconductor layer. A first channel is provided between the source and the drain. Carbon nanotubes are provided in the first channel. A second channel is provided between the drain and the gate. An ion gel is provided in the second channel. By regulating a composition of the ion gel and a content of a dopant, a threshold voltage of a carbon nanotube thin film transistor is effectively controlled.

An array substrate and a manufacturing method thereof, a display panel and a display device are provided. The array substrate includes: a base substrate including a driving thin film transistor region and a switching thin film transistor region; and a buffer layer containing oxygen, the buffer layer including a first buffer part located in the driving thin film transistor region and a second buffer part located in the switching thin film transistor region; the first buffer part has a first thickness, the second buffer part has a second thickness, and the second thickness is greater than the first thickness.

A technology called RINSE (Removal of Incubated Nanotubes through Selective Exfoliation) is demonstrated. RINSE removes carbon nanotube (CNT) aggregates in CNFETs without compromising CNFET performance. In RINSE, CNTs are deposited on a substrate, coated with a thin adhesive layer, and sonicated. The adhesive layer is strong enough to keep the individual CNTs on the substrate, but not the larger CNT aggregates. When combined with a CNFET CMOS process as disclosed here, record CNFET CMOS yield and uniformity can be realized.