A solid-state imaging apparatus includes a pixel array in which a plurality of pixels are two-dimensionally arranged, wherein each pixel has a first photoelectric conversion region formed above a semiconductor layer, a second photoelectric conversion region formed in the semiconductor layer, a first filter configured to transmit a light in a predetermined wavelength region corresponding to a color component, and a second filter having different transmission characteristics from the first filter. One photoelectric conversion region out of the first photoelectric conversion region and the second photoelectric conversion region photoelectrically converts light in a visible light region, the other photoelectric conversion region photoelectrically converts light in an infrared region, the first filter is formed above the first photoelectric conversion region, and the second filter has transmission characteristics of making wavelengths of lights in an infrared region absorbed in the other photoelectric conversion region formed below the first filter the same.

Three-dimensional (3D) semiconductor memory devices are provided. A 3D semiconductor memory device includes an electrode structure on a substrate. The electrode structure includes gate electrodes stacked on the substrate. The gate electrodes include electrode pad regions. The 3D semiconductor memory device includes a dummy vertical structure penetrating one of the electrode pad regions. The dummy vertical structure includes a dummy vertical semiconductor pattern and a contact pattern extending from a portion of the dummy vertical semiconductor pattern toward the substrate.

According to an embodiment, a photodetector includes a first photoelectric conversion element, a second photoelectric conversion element, and an absorption layer. The first photoelectric conversion element includes a first photoelectric conversion layer for converting energy of radiation into electric charges. The second photoelectric conversion element includes a second photoelectric conversion layer for converting energy of radiation into electric charges. The absorption layer is arranged between the first photoelectric conversion element and the second photoelectric conversion element to absorb radiation having energy equal to or lower than a threshold value.

An alternating stack of insulating layers and spacer material layers is formed over a substrate. Each of the first insulating layers and the first sacrificial material layers includes a respective horizontally-extending portion and a respective non-horizontally-extending portion. Memory stack structures are formed through the horizontally-extending portions of the alternating stack. Regions of the non-horizontally-extending portions of the sacrificial material layers are masked with patterned etch mask portions. Unmasked first regions of the non-horizontally-extending portions of the first sacrificial material layers are selectively recessed, and the sacrificial material layers with electrically conductive layers. Each electrically conductive layer can include a vertical plate region and a protrusion region that protrudes above the vertical plate region and having a narrower lateral dimension that the vertical plate region. Metal contact structures can be formed on the protrusion regions without contacting the vertical plate regions.

A metal oxide semiconductor carbon nanotube thin film transistor circuit includes a p-type carbon nanotube thin film transistor and an n-type carbon nanotube thin film transistor stacked on one another. The p-type carbon nanotube thin film transistor includes a first semiconductor carbon nanotube layer, a first drain electrode, a first source electrode, a functional dielectric layer, and a first gate electrode. The n-type carbon nanotube thin film transistor includes a second semiconductor carbon nanotube layer, a second drain electrode, a second source electrode, a first insulating layer, and a second gate electrode. The first drain electrode and the second drain electrode are electrically connected with each other. The first gate electrode and the second gate electrode are electrically connected with each other.

Generally discussed herein are systems, devices, and methods for data interpolation. A system for data interpolation can include first circuitry to split a set of data into four disjoint subsets including first, second, third, and fourth subsets and load each of the disjoints subsets into respective first, second, third, and fourth memory portions, second circuitry to retrieve, simultaneously, data from each of the first, second, third, and fourth memory portions, and interpolation circuitry to perform, based on the retrieved data, data interpolation.

A method for making a metal oxide semiconductor carbon nanotube thin film transistor circuit. A p-type carbon nanotube thin film transistor and a n-type carbon nanotube thin film transistor are formed on an insulating substrate and stacked with each other. The p-type carbon nanotube thin film transistor includes a first semiconductor carbon nanotube layer, a first drain electrode, a first source electrode, a functional dielectric layer, and a first gate electrode. The n-type carbon nanotube thin film transistor includes a second semiconductor carbon nanotube layer, a second drain electrode, a second source electrode, a first insulating layer, and a second gate electrode. The first drain electrode and the second drain electrode are electrically connected with each other. The first gate electrode and the second gate electrode are electrically connected with each other.

Disclosed is a 3D static RAM core cell having a vertically stacked structure, including six thin-film transistors each having a gate electrode, a source electrode and a drain electrode, the static RAM core cell including two switching thin-film transistors, each connected to a bit line and a word line to select recording and reading of data, and four data-storage thin-film transistors connected to a power supply voltage (Vdd) or a ground voltage (Vss) to record and read data, the static RAM core cell including a first transistor layer including two thin-film transistors selected from among the six thin-film transistors, a second transistor layer disposed on the first transistor layer and including two thin-film transistors selected from among the remaining four thin-film transistors, and a third transistor layer disposed on the second transistor layer and including the remaining two thin-film transistors, at least one electrode of the first transistor layer and at least one electrode of the second transistor layer being electrically connected to each other, and at least one electrode of the second transistor layer and at least one electrode of the third transistor layer being electrically connected to each other. Thereby, the static RAM core cell is configured such that organic transistors of the same type are arranged in the same plane and are vertically stacked, thus omitting a complicated patterning process for forming organic transistors of different types upon fabrication of a memory element, and also reducing the area occupied by the memory element to thereby increase the degree of integration of semiconductor circuits.

This technology relates to an imaging apparatus and an electronic device structured to perform pupil correction appropriately. There are provided a photoelectric conversion film configured to absorb light of a predetermined color component to generate signal charges, a first lower electrode configured to be formed under the photoelectric conversion film, a second lower electrode configured to be connected with the first lower electrode, a via configured to connect the first lower electrode with the second lower electrode, and a photodiode configured to be formed under the second lower electrode and to generate signal charges reflecting the amount of incident light. A first distance between the center of the photodiode and the center of the via at the center of the angle of view is different from a second distance therebetween at an edge of the angle of view. The present technology can be applied to imaging apparatuses.

A semiconductor apparatus includes a plurality of semiconductor devices. The semiconductor devices each include a ferroelectric layer, a conductive metal oxide layer, and a semiconductor layer, between two electrodes. The conductive metal oxide layer may be between the ferroelectric layer and the semiconductor layer. The ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer may all include a metal oxide. The conductive metal oxide layer may include one or more materials selected from the group consisting of an indium oxide, a zinc oxide, a tin oxide, and any combination thereof.