Disclosed are memory cells that include a mixture of an acrylic polyol, an alkylene urea-glyoxal resin, and an acid catalyst, and memory devices that contain a plurality of memory cells.

A memory device according to an embodiment includes a first conductive layer, a second conductive layer, a variable resistance layer disposed between the first conductive layer and the second conductive layer, and an organic molecular layer disposed between the variable resistance layer and the second conductive layer and containing organic molecules. Each of the organic molecules includes a first fused polycyclic unit having a first HOMO level, a second fused polycyclic unit having a second HOMO level higher in energy than the first HOMO level, and a third fused polycyclic unit disposed between the first fused polycyclic unit and the second fused polycyclic unit. The third fused polycyclic unit has a third HOMO level higher in energy than the first HOMO level and the second HOMO level.

Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed.

A neuromorphic device is provided. The neuromorphic device may include a pre-synaptic neuron; a row line extending in a row direction from the pre-synaptic neuron; a post-synaptic neuron; a column line extending in a column direction from the post-synaptic neuron; and a synapse disposed at an intersection between the row line and the column line. The synapse may include a first synapse layer including a plurality of first carbon nano-tubes; a second synapse layer including a plurality of second carbon nano-tubes having different structures from the plurality of first carbon nano-tubes; and a third synapse layer including a plurality of third carbon nano-tubes having different structures from the plurality of first carbon nano-tubes and the plurality of second carbon nano-tubes.

A semiconductor memory device according to an embodiment includes a semiconductor layer, a control gate electrode, and an organic molecular layer provided between the semiconductor layer and the control gate electrode, and the organic molecular layer having an organic molecule that includes a molecular structure described by a molecular formula (1): ##STR00001##

A molecular memory recording molecular polarization of a single-molecule electret, and the single-molecule electret includes a cluster skeleton 100 having a continuous hole 101 and a plurality of stable ionic sites 102a, 102b and a metal ion M. The molecular polarization is shown in a state in which the metal ion is included in the stable ionic site. The molecular polarization is changed by movement of the metal ion to the other hollow stable ionic site by application of an electric field. The recordkeeping time of the molecular memory in a temperature range of 100 C. to 100 C. based on the ion radius of the metal ion is 3.010.sup.2 seconds to 9.110.sup.22 seconds. Based on the recordkeeping time, the molecular memory is used as any of a volatile memory, a non-volatile memory, and a storage class memory.

The present disclosure is directed toward carbon based diodes, carbon based resistive change memory elements, resistive change memory having resistive change memory elements and carbon based diodes, methods of making carbon based diodes, methods of making resistive change memory elements having carbon based diodes, and methods of making resistive change memory having resistive change memory elements having carbons based diodes. The carbon based diodes can be any suitable type of diode that can be formed using carbon allotropes, such as semiconducting single wall carbon nanotubes (s-SWCNT), semiconducting Buckminsterfullerenes (such as C60 Buckyballs), or semiconducting graphitic layers (layered graphene). The carbon based diodes can be pn junction diodes, Schottky diodes, other any other type of diode formed using a carbon allotrope. The carbon based diodes can be placed at any level of integration in a three dimensional (3D) electronic device such as integrated with components or wiring layers.

A conjugated polymer layer with a built-in diode is formed by providing a first metal-chalcogenide layer over a bottom electrode. Subsequently, a second metal-chalcogenide layer is provided over and in contact with the first metal-chalcogenide layer. The first metal-chalcogenide layer has a first conductivity type and the second metal-chalcogenide layer has a second conductivity type. The plane of contact between the first and second metal-chalcogenide layers creates the p-n junction of the built-in diode. Then a polymer layer is selectively deposited on the second metal-chalcogenide layer. The second metal-chalcogenide layer provides ions to the polymer layer to change its resistivity. A top electrode is then provided over the polymer layer. An exemplary memory cell may have the following stacked structure: first electrode/n-type semiconductor/p-type semiconductor/conjugated polymer/second electrode.

The present disclosure generally relates to multi-switch storage cells (MSSCs), three-dimensional MSSC arrays, and three-dimensional MSSC memory. Multi-switch storage cells include a cell select device, multiple resistive change elements, and an intracell wiring electrically connecting the multiple resistive change elements together and to the cell select device. MSSC arrays are designed (architected) and operated to prevent inter-cell (sneak path) currents between multi-switch storage cells, which prevents stored data disturb from adjacent cells and adjacent cell data pattern sensitivity. Additionally, READ and WRITE operations may be performed on one of the multiple resistive change elements in a multi-switch storage cell without disturbing the stored data in the remaining resistive change elements. However, controlled parasitic currents may flow in the remaining resistive change elements within the cell. Isolating each multi-switch storage cell in a three-dimensional MSSC array, enables in-memory computing for applications such as data processing for machine learning and artificial intelligence.

Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed.