Patent classifications
H10K19/202
Resistive change elements using passivating interface gaps and methods for making same
A method to fabricate a resistive change element. The method may include forming a stack over a substrate. The stack may include a conductive material, a resistive change material, a first surface, and a second surfaces opposite the first surface. The method may further include depositing a first material over the stack such that the first material directly contacts at least one of the first surface and the second surface of the stack. The method may also include after depositing the first material, forming a second material over the first material and evaporating a portion of the first material through the second material to create a gap between the second material and the at least one of the first surface and the second surface of the stack.
Cross-Point Array of Polymer Junctions with Individually-Programmed Conductances
Programmable memory devices having a cross-point array of polymer junctions with individually-programmed conductances are provided. In one aspect, a method of forming a memory device includes: forming first metal lines on an insulating substrate; forming polymeric resistance elements on the first metal lines; and forming second metal lines over the polymeric resistance elements with a single one of the polymeric resistance elements present at each intersection of the first/second metal lines forming a cross-point array. A memory device and a method of operating a memory device are also provided.
Reducing error rates with alpha particle protection
An integrated circuit package with a buffer providing radiation protection to memory elements and components is described. The integrated circuit packages and the incorporated buffers provide a protective distance between potential sources of internal radiation particles within the integrated circuit package and any memory elements/components which may be sensitive to radiation such as alpha particles. This protective distance allows for the integrated circuit packages to be completed or assembled without needing added more expensive or redundant memory components.
ELECTRONIC SWITCHING ELEMENT
An electronic switching element is described having, in sequence, a first electrode, a molecular layer bonded to a substrate, and a second electrode. The molecular layer contains compounds of formula I, R.sup.1-(A.sup.1-Z.sup.1).sub.r—B.sup.1—(Z.sup.2-A.sup.2).sub.s-Sp-G, wherein A.sup.1, A.sup.2, B.sup.1, Z.sup.1, Z.sup.2, Sp, G, r, and s are as defined herein, in which a mesogenic radical is bonded to the substrate via a spacer group, Sp, by means of an anchor group, G. The switching element is suitable for production of components that can operate as a memristive device for digital information storage.
MEMORY INCLUDING A SELECTOR SWITCH ON A VARIABLE RESISTANCE MEMORY CELL
Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed.
METHOD FOR PRODUCING AN ELECTRONIC COMPONENT WHICH INCLUDES A SELF-ASSEMBLED MONOLAYER
The invention relates to a process for the production of an electronic component comprising a self-assembled monolayer (SAM) using compounds of the formula I
R.sup.1-(A.sup.1-Z.sup.1).sub.r—(B.sup.1).sub.n—(Z.sup.2-A.sup.2).sub.s-Sp-G (I)
in which the groups occurring have the meanings defined in claim 1; the present invention furthermore relates to the use of the components in electronic switching elements and to compounds for the production of the SAM.
Memory cell and forming method thereof
A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part. The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.
Josephson toroidal vortex quantum superconductive/memcapacitive and superconductive/memristive devices of making and their applications at room temperature thereto
Multiple Josephson toroidal vertex quantum superconductive/memristive and superconductive/memcapacitive devices were invented with various superlattice structures, which work at room temperature without an applied external magnetic flux. The first type of the superlattices of the devices comprises of multiple-layers of organometallic polymers on gold chips by self-assembling that mimics the function of Matrix Metalloproteinase-2 (MMP-2). Another type of quantum superconductor/memristor comprises of multiple-organic polymers cross-linked with MMP-2 protein forming Josephson toroidal vertex on the gold surface. Models of the quantum superconductive/memristive and superconductive/memcapacitive devices were fabricated in nano superlattice structures and the devices module configurations were described. Three different methods were used to evaluate the devices' applications in sub fg/mL collagen-1 sensing, energy storage, and the super-position characteristics as a potential quantum bit device. The superconductivity, memristive, and memcapacitive functions were also evaluated in multiple methods, respectively.
Cross-point array of polymer junctions with individually-programmed conductances
Programmable memory devices having a cross-point array of polymer junctions with individually-programmed conductances are provided. In one aspect, a method of forming a memory device includes: forming first metal lines on an insulating substrate; forming polymeric resistance elements on the first metal lines; and forming second metal lines over the polymeric resistance elements with a single one of the polymeric resistance elements present at each intersection of the first/second metal lines forming a cross-point array. A memory device and a method of operating a memory device are also provided.
REDUCING ERROR RATES WITH ALPHA PARTICLE PROTECTION
An integrated circuit package with a buffer providing radiation protection to memory elements and components is described. The integrated circuit packages and the incorporated buffers provide a protective distance between potential sources of internal radiation particles within the integrated circuit package and any memory elements/components which may be sensitive to radiation such as alpha particles. This protective distance allows for the integrated circuit packages to be completed or assembled without needing added more expensive or redundant memory components.