Embodiments of the present disclosure provide a display panel comprising a plurality of first connecting lines and a plurality of second connecting lines which are cross-arranged, a first insulation layer, a second insulation layer defining first holes extending through the first insulation layer and the second insulation layer and second holes extending through the second insulation layer, and a plurality of third connecting lines, wherein each of the plurality of the third connecting lines is electrically connected to a corresponding one of the plurality of the first connecting lines via a corresponding one of the first hole and is electrically connected to a corresponding one of the plurality of the second connecting lines via a corresponding one of the second hole, and each of the second holes does not overlap the plurality of the first connecting lines in a top view.

A method of manufacturing a display device includes: the measurement step of sweeping a voltage to light-emitting elements and measuring a current value that flows in the light-emitting elements in response to a voltage value applied; the computation step of computing a first derivative value of the current value with respect to the voltage value, the first derivative value representing voltage dependence of a first derivative of the current value; the peak determination step of determining a peak of the first derivative value; the processing step of processing the light-emitting elements based on a result of the peak determination step; and the attaching step of attaching a housing to the substrate.

An electronic panel includes a base substrate having a first area, a second area adjacent to the first area, and a third area adjacent to the second area, a plurality of pixels in the second area, a plurality of pixel signal lines in the third area and connected to the pixels, a crack detecting pattern spaced apart from the pixels and in the first area, a first line spaced apart from the pixel signal lines, in the third area, and connected to a portion of the crack detecting pattern, and a second line spaced apart from the pixel signal lines, in the third area, connected to another portion of the crack detecting pattern, and spaced apart from the first line. The crack detecting pattern has a line-symmetrical shape with respect to a symmetry axis passing through a center of the first area.

A display substrate and a display apparatus are provided, the display substrate includes a base substrate including a display region and a peripheral region; the display region includes multiple sub-pixels, multiple data lines and multiple power supply lines; the peripheral region includes at least one test data signal line, at least one test control signal line and multiple test units, the multiple test units are at a side of the multiple data lines away from the display region, and at least one of the multiple test units is electrically connected with at least one of the multiple data lines, the at least one test data signal line, and the at least one test control signal line; the peripheral region further includes a first power supply bus and multiple connecting parts, the first power supply bus is at a side of the multiple test units away from the display region.

A display apparatus including a substrate; a display area arranged on the substrate and including a plurality of pixels, and a peripheral area arranged outside the display area; a dam surrounding the display area; a crack detector arranged between the dam and an end of the substrate and electrically connected to at least one of the plurality of pixels; a crack prevention dam arranged between the dam and the end of the substrate; and an encapsulation layer including a first inorganic layer, an organic layer, and a second inorganic layer, each covering the display area and a portion of the peripheral area. The first inorganic layer and the second inorganic layer in the encapsulation layer extend to the end of the substrate.

A display apparatus includes a substrate with a first area and a second area outside the first area, a plurality of pixels located in the first area, a power supply line located in the second area and having a through-hole penetrating the power supply line, a first insulating layer covering the power supply line and filling the through-hole thereof, a test pad located on the first insulating layer and electrically insulated from the power supply line, wherein the test pad overlaps a region defined by the through-hole, a second insulating layer covering the test pad, and a bridge located on the second insulating layer and electrically insulated from the test pad, and electrically connected to the power supply line via a first contact hole in the first insulating layer and the second insulating layer. The test pad is disposed beneath the bridge.

A method of analyzing film on a substrate comprises receiving surface profile data obtained from measurements of a substrate having a plurality of discrete regions with one or more film layers; extracting, based on a predetermined pattern of the discrete regions, a plurality of parameters from the received surface profile data, the plurality of parameters comprising one or more parameters of a film layer of each discrete regions, and displaying a user interface. The user interface may comprise a plurality of individual graphs each illustrating the one or more parameters of the one or more film layers for a corresponding subset of the plurality of discrete regions, and a composite graph illustrating the one or more parameters of the one or more film layers for each discrete region of the plurality of discrete regions, wherein the composite graph corresponds to the plurality of individual graphs being overlaid together.

A method of analyzing film on a substrate comprises receiving surface profile data obtained from measurements of a substrate having a plurality of discrete regions with one or more film layers; extracting, based on a predetermined pattern of the discrete regions, a plurality of parameters from the received surface profile data, the plurality of parameters comprising one or more parameters of a film layer of each discrete regions, and displaying a user interface. The user interface may comprise a plurality of individual graphs each illustrating the one or more parameters of the one or more film layers for a corresponding subset of the plurality of discrete regions, and a composite graph illustrating the one or more parameters of the one or more film layers for each discrete region of the plurality of discrete regions, wherein the composite graph corresponds to the plurality of individual graphs being overlaid together.

A display apparatus includes a printed circuit board including first to fourth output pad regions and a flexible circuit board having a first end connected to a display panel and a second end connected to the printed circuit board. The first output pad region includes a 1.sup.st-1.sup.st output pad group and a 1.sup.st-2.sup.nd output pad group, the second output pad region includes a 2.sup.nd-1.sup.st output pad group and a 2.sup.nd-2.sup.nd output pad group, the fourth output pad region includes a 4.sup.th- 1.sup.st output pad group and a 4.sup.th-2.sup.nd output pad group, and the printed circuit board includes a first input terminal electrically connected to the 1.sup.st-1.sup.st output pad group, a second input terminal electrically connected to the 2.sup.nd-2.sup.nd output pad group, a third input terminal electrically connected to the first input terminal, and a fourth input terminal electrically connected to the 4.sup.th-2.sup.nd output pad group.

A method of fabricating an array substrate is provided. The method includes providing a substrate including a gate pad configured to bond a gate driving integrated circuit, a data pad configured to bond a data driving integrated circuit, and a plurality of peripheral layout gate (PLG) proto-lines connecting the gate pad and the data pad; forming a PLG testing pad on the substrate; forming a shorting bar connecting the PLG testing pad to first terminals of the plurality of PLG proto-lines; forming a plurality of testing pins respectively connected to second terminals of the plurality of PLG proto-lines, wherein the plurality of testing pins are formed in a first dummy region of the substrate, the first dummy region is adjacent to an array substrate region of the substrate; and connecting the plurality of testing pins to a probe unit to test connectivity of the plurality of PLG proto-lines.