A power generation element includes: a substrate including mutually opposed first and second principal surfaces; an electrode portion provided on the first principal surface and the second principal surface, the electrode portion including a first electrode portion and a second electrode portion; and an intermediate portion including nanoparticles. The substrate includes a first substrate portion and a second substrate portion that are mutually overlapped viewed in a first direction. The first principal surface of the first substrate portion includes a first separated surface and a first joint surface. The second principal surface of the second substrate portion includes a second separated surface and a second joint surface.

A thermoelectric cooler, a method for preparing a thermoelectric cooler, and an electronic device. The thermoelectric cooler includes two monocrystalline silicon substrates disposed opposite to each other and a plurality of semiconductor thermoelectric particles located between the two monocrystalline silicon substrates. An insulation layer is provided on a side that is of a monocrystalline silicon substrate and that faces the semiconductor thermoelectric particles. A conductive sheet is provided between the insulation layer and the semiconductor thermoelectric particles, and the conductive sheet is electrically connected to the semiconductor thermoelectric particles, so that the semiconductor thermoelectric particles form a serial connection circuit.

Operations for integrating thermoelectric devices in Fin FET technology may be implemented in a semiconductor device having a thermoelectric device. The thermoelectric device includes a substrate and a fin structure disposed on the substrate. The thermoelectric device includes a first connecting layer and a second connecting layer disposed on opposing ends of the fin structure. The thermoelectric device includes a first thermal conductive structure thermally and a second thermal conductive structure thermally coupled to the opposing ends of the fin structure. The fin structure may be configured to transfer heat from one of the first thermal conductive structure or the second thermal conductive structure to the other thermal conductive structure based on a direction of current flow through the fin structure. In this regard, the current flow may be adjusted by a power circuit electrically coupled to the thermoelectric device.

A thermoelectric material of the present invention includes copper, tin, and sulfur, wherein a ratio A/B of the number A of copper atoms to the number B of tin atoms is 0.5 to 2.5 and a content of a metal element other than copper and tin is 5 mol % or less with respect to total metal elements. Additionally, the thermoelectric material of the present invention has a thermal conductivity less than 1.0 W/(m.Math.K) at 200 to 400° C.

Composite nanoparticle compositions and associated nanoparticle assemblies are described herein which, in some embodiments, exhibit enhancements to one or more thermoelectric properties including increases in electrical conductivity and/or Seebeck coefficient and/or decreases in thermal conductivity. In one aspect, a composite nanoparticle composition comprises a semiconductor nanoparticle including a front face and a back face and sidewalls extending between the front and back faces. Metallic nanoparticles are bonded to at least one of the sidewalls establishing a metal-semiconductor junction.

A memory device comprises multiple memory dice arranged vertically in a stack of memory dice and at least one thermoelectric die contacting the bulk silicon layer of at least one of the memory dice of the multiple memory dice. Each memory die of the multiple memory dice includes an active circuitry layer that includes memory cells of a memory array and a bulk silicon layer. The thermoelectric die is configured to one or both of reduce heat from the memory die when a current is applied to terminals of the thermoelectric die and generate a voltage at the terminals of the thermoelectric die when heat from the memory die is applied to the thermoelectric die.

On-die temperature control for semiconductor die assemblies, and associated systems and methods are disclosed. In an embodiment, a semiconductor device assembly includes first and second semiconductor dies directly bonded to each other. The semiconductor dies each includes conductive pads and resistive heating components in a dielectric layer, where the resistive heating components are located proximate to the conductive pads to supply localized thermal energy to the conductive pads in response to electric current flowing through the resistive heating components. In some embodiments, the conductive pads of the first semiconductor die are directly bonded to the conductive pads of the second semiconductor die at a first temperature less than a second temperature for the thermal expansion of the conductive pads absent the localized thermal energy generated by the resistive heating components.

A method for manufacturing a thermoelectric conversion element includes forming a thermoelectric film containing a thermoelectric material on a surface of a substrate, pressing the thermoelectric film with a mold to form a pattern of the thermoelectric film on the surface of the substrate, and heating the pattern of the thermoelectric film formed on the surface of the substrate to generate the thermoelectric conversion element.

Disclosed is a composition for forming a thermoelectric film, the composition comprising an edge-oxidized graphene oxide, wherein the edge-oxidized graphene oxide is dispersed in a thermoelectric material.

A thermoelectric coating containing “p” and “n” semiconductor elements in the form of non-contacting layers, which are arranged alternately with each other, so that between the “p” layers there is a “n” layer, with the “p” and “n” layers “n” are connected to each other in series with conductive elements with connection terminals for the output of the generated electrical energy, and containing an electrical insulator layer, is characterized in that a layer (2a) of an electrical insulator with a thickness of at least 200 nm is applied to the substrate (1), with layers of conductive elements (3a) with a thickness of 200 nm to 5 .Math.m, on which semiconductor layers “p” and “n” with a thickness of 50 nm to 5 .Math.m and a width of 0.1 mm to 5 mm are applied.