A cross-plane flexible micro-TEG with hundreds of pairs of thermoelectric pillars formed via electroplating, microfabrication, and substrate transferring processes is provided herein. Typically, fabrication is conducted on a Si substrate, which can be easily realized by commercial production line. The fabricated micro-TEG transferred to the flexible layer from the Si substrate. Fabrication methods provided herein allow fabrication of main TEG components including bottom interconnectors, thermoelectric pillars, and top interconnectors by electroplating. Such flexible micro-TEGs provide high output power density due to high density of thermoelectric pillars and very low internal resistance of electroplated components. The flexible micro-TEG can achieve a power per unit area of 4.5 mW cm.sup.2 at a temperature difference of 50 K, which is comparable to performance of flexible TEGs developed by screen printing. The power per unit weight of flexible TEGs described herein is as high as 60 mW g.sup.1, which is advantageous for wearable applications.

Disclosed are apparatus and methodology for constructing thermoelectric devices (TEDs). N-type elements are paired with P-type elements in an array of pairs between substrates. The paired elements are electrically connected in series by various techniques including brazing for hot side and/or also cold side connections, and soldering for cold side connections while being thermally connected in parallel. In selected embodiments, electrical and mechanical connections of the elements may be made solely by mechanical pressure.

A thermoelectric element, particularly for a thermoelectric converter, includes an assembly of constituent layers comprising a central layer made of p- or n-type thermoelectric material, then, in an assembly direction, and on each side of said central layer, an intermediate layer forming a diffusion barrier followed by a buffer layer made of composite metal material. The buffer layers are intended to be secured to metal electrodes, characterized in that the cumulative thickness of the two buffer layers is greater than or equal to 50% of the thickness of the central layer, and preferably greater than or equal to 100% of the thickness of the central layer and very preferably greater than or equal to 200% of the thickness of the central layer, and in that the constituent material of the buffer layers is an alloy of two metals chosen from the family: Ti.sub.xAg.sub.1-x, V.sub.xFe.sub.1-x, V.sub.xAg.sub.1-x, Ti.sub.xFe.sub.1-x, where 0<x<1.

A semiconductor package includes a frame having a through-hole, a semiconductor chip disposed in the through-hole of the frame, and having an active surface on which a connection pad is disposed and an inactive surface opposite to the active surface, a thermoelectric device disposed on the inactive surface of the semiconductor chip, in the through-hole of the frame, and including a semiconductor layer and an electrode layer connected to the semiconductor layer, an encapsulant sealing at least portions of the semiconductor chip and the thermoelectric device, and a first connection structure disposed on the active surface of the semiconductor chip, and including a first redistribution layer electrically connected to the connection pad of the semiconductor chip.

An integrated circuit (IC) package comprising an IC die, the IC die having a first surface and an opposing second surface. The IC die comprises a semiconductor material. The first surface comprises an active layer. A thermoelectric cooler (TEC) comprising a thermoelectric material is embedded within the IC die between the first surface and the second surface and adjacent to the active layer. The TEC has an annular shape that is substantially parallel to the first and second surfaces of the IC die. The thermoelectric material is confined between an outer sidewall along an outer perimeter of the TEC and an inner sidewall along an inner perimeter of the TEC. The outer and inner sidewalls are substantially orthogonal to the first and second surfaces of the IC die.

A thermoelectric generator includes a hot side heat exchanger, a cold side heat exchanger, a plurality of n-type semiconductor legs arranged between the hot side heat exchanger and the cold side heat exchanger, and a plurality of p-type semiconductor legs arranged between the hot side heat exchanger and the cold side heat exchanger and alternating electrically in series with the plurality of n-type semiconductor legs. At least one of the plurality of n-type semiconductor legs and the plurality of p-type semiconductor legs is formed of an alloy having a half-Heusler structure and comprising Si and Sn with molar fractions of x Sn and 1x Si, and x is less than 1.

The presently disclosed subject matter provides thermoelectric power generating systems that can include an arrangement of power generator units electrically connected to provide a global output voltage, each power generator unit generating an individual output voltage, and an electronic stabilization system. The electronic stabilization system can include DC/DC converters connected to one or more of the power generator units; electrical variable detectors including at least one of voltage detectors and current detectors for automatically measuring the individual voltage or individual current existing at a point of a DC/DC converter; and a microprocessor-based controller connected to the voltage and/or current detectors to receive the measured voltages and/or currents, and, based on the measurements, to control the operation of the DC/DC converters to obtain desired DC/DC converter output voltages and/or desired DC/DC converter currents.

A multilevel thermoelectric cooling (TEC) stack channels thermal power away from an element to be cooled which is mounted on a substrate such as a circuit board and may generate an intrinsic heat load. The TEC stack has an inner TEC level which is in direct or indirect thermal contact with the element and an outer TEC level. At least one of the TEC levels includes a shaped thermal guard ring which is in thermal contact with the substrate. The thermal guard ring(s) define isothermal boundaries on the substrate, and effectively channel, or wick, thermal power away from the element to be cooled.

A housing for a thermoelectric module can stably protect individual elements of the thermoelectric module such as thermoelectric elements, electrodes, and insulating boards, while maintaining power generation performance of the thermoelectric module. The housing for a thermoelectric module includes: a housing enveloping at least one thermoelectric module; and a heat barrier unit configured to prevent a flow of heat from being transferred through a sidewall of the housing.

The present disclosure is related to structures for and methods for producing thermoelectric devices. The thermoelectric devices include multiple stages of thermoelements. Each stage includes alternating n-type and p-type thermoelements. The stages are sandwiched between upper and lower sets of metal links fabricated on a pair of substrate layers. The metal links electrically connect pairs of n-type and p-type thermoelements from each stage. There may be additional sets of metal links between the multiple stages. The individual thermoelements may be sized to handle differing amounts of electric current to optimize performance based on their location within the multistage device.