A method for manufacturing a semiconductor structure includes: providing a substrate; forming a first shielding layer on the substrate; forming a first electrode penetrating the first shielding layer; forming a storage structure on the first electrode; forming a second shielding layer on the top surface and sidewalls of the storage structure, wherein the first shielding layer and the second shielding layer combine into one integrated shielding layer; and forming a second electrode which penetrates the shielding layer and electrically connects to the storage structure.

A method for manufacturing a semiconductor structure includes: providing a substrate; forming a first shielding layer on the substrate; forming a first electrode penetrating the first shielding layer; forming a storage structure on the first electrode; forming a second shielding layer on the top surface and sidewalls of the storage structure, wherein the first shielding layer and the second shielding layer combine into one integrated shielding layer; and forming a second electrode which penetrates the shielding layer and electrically connects to the storage structure.

A magnetic storage element and an electronic apparatus having a reduced writing current while retaining a magnetism retention property of a storage layer. The magnetic storage element includes a spin orbit layer extending in one direction, a writing line that is electrically coupled to the spin orbit layer, and allows a current to flow in an extending direction of the spin orbit layer, a tunnel junction element including a storage layer, an insulator layer, and a magnetization fixed layer that are stacked in order on the spin orbit layer, and a non-magnetic layer having a film thickness of 2 nm or less, and disposed at any stack position between the spin orbit layer and the insulator layer.

Embodiments of magnetic tunnel junction (MTJ) structures discussed herein employ seed layers of one or more layer of chromium (Cr), NiCr, NiFeCr, RuCr, IrCr, or CoCr, or combinations thereof. These seed layers are used in combination with one or more pinning layers, a first pinning layer in contact with the seed layer can contain a single layer of cobalt, or can contain cobalt in combination with bilayers of cobalt and platinum (Pt), iridium (Ir), nickel (Ni), or palladium (Pd), The second pinning layer can be the same composition and configuration as the first, or can be of a different composition or configuration. The MTJ stacks discussed herein maintain desirable magnetic properties subsequent to high temperature annealing.

A method of manufacturing a memory device includes sequentially forming a first magnetization layer, a tunnel barrier layer, and a second magnetization layer on each other; forming a magnetic tunnel junction structure by patterning the first magnetization layer, the tunnel barrier layer, and the second magnetization layer; forming a sidewall metal layer by etching a portion of a redeposited metal covering a sidewall of the magnetic tunnel junction structure; performing an oxidizing operation that includes oxidizing an exposed surface of the sidewall metal layer to provide an oxidized sidewall metal layer; and performing an irradiating operation that includes irradiating an ion beam towards the oxidized sidewall metal layer. A sidewall insulating layer covering a sidewall of the magnetic tunnel junction structure is formed by alternately performing the oxidizing operation and the irradiating operation two or more times.

A method of manufacturing a memory device includes sequentially forming a first magnetization layer, a tunnel barrier layer, and a second magnetization layer on each other; forming a magnetic tunnel junction structure by patterning the first magnetization layer, the tunnel barrier layer, and the second magnetization layer; forming a sidewall metal layer by etching a portion of a redeposited metal covering a sidewall of the magnetic tunnel junction structure; performing an oxidizing operation that includes oxidizing an exposed surface of the sidewall metal layer to provide an oxidized sidewall metal layer; and performing an irradiating operation that includes irradiating an ion beam towards the oxidized sidewall metal layer. A sidewall insulating layer covering a sidewall of the magnetic tunnel junction structure is formed by alternately performing the oxidizing operation and the irradiating operation two or more times.

A method for fabricating a semiconductor device includes the steps of: forming a first metal interconnection on a substrate; forming a stop layer on the first metal interconnection; removing the stop layer to form a first opening; forming an electromigration enhancing layer in the first opening; and forming a second metal interconnection on the electromigration enhancing layer. Preferably, top surfaces of the electromigration enhancing layer and the stop layer are coplanar.

A metallic hardmask is formed having a selected stress designed to create a selected amount of positive wafer bow. In preferred embodiments, metallic hardmask is disposed on a memory pillar layer over a wafer substrate. A set of memory pillars using the metal hardmask. Because of the positive wafer bow, the patterned set of memory pillars at both the edges and the central portion of the wafer substrate are aligned with a respective contact for a memory device. A positive wafer bow is defined as a bowed wafer substrate where a central portion of a patterned side of the wafer substrate is lower than edges of the wafer substrate.

A metallic hardmask is formed having a selected stress designed to create a selected amount of positive wafer bow. In preferred embodiments, metallic hardmask is disposed on a memory pillar layer over a wafer substrate. A set of memory pillars using the metal hardmask. Because of the positive wafer bow, the patterned set of memory pillars at both the edges and the central portion of the wafer substrate are aligned with a respective contact for a memory device. A positive wafer bow is defined as a bowed wafer substrate where a central portion of a patterned side of the wafer substrate is lower than edges of the wafer substrate.

A memory device is provided that includes at least one MTJ pillar which can have a ternary program state as compared to a binary program state in a conventional device. The MTJ pillar contains a lower MTJ structure that includes at least a first magnetic reference material, a first tunnel barrier and a first magnetic free layer material, and an upper MTJ structure that includes at least a second magnetic reference material, a second tunnel barrier and a second magnetic free layer material; the upper MTJ structure is stacked atop the lower MTJ structure. The first and second magnetic free layer materials have different designs and/or compositions resulting in different switching voltages.