A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.

A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

An electronic device may include a semiconductor memory, and the semiconductor memory may include a substrate; a variable resistance element formed over the substrate and exhibiting different resistance values representing different digital information, the variable resistance element including a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer; and a blocking layer disposed on at least sidewalls of the variable resistance element, wherein the blocking layer may include a layer that is substantially free of nitrogen, oxygen or a combination thereof.

An electronic device may include a semiconductor memory, and the semiconductor memory may include a substrate; a variable resistance element formed over the substrate and exhibiting different resistance values representing different digital information, the variable resistance element including a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer; and a blocking layer disposed on at least sidewalls of the variable resistance element, wherein the blocking layer may include a layer that is substantially free of nitrogen, oxygen or a combination thereof.

Semiconductor device includes pair of active devices, composite spin Hall electrode, and a magnetic tunnel junction. Composite spin Hall electrode is electrically connected to pair of active devices. Magnetic tunnel junction is disposed on opposite side of composite spin hall electrode with respect to pair of active devices. Spin Hall electrode includes pair of heavy metal layers, and spacer layer disposed in between pair of heavy metal layers. Pair of heavy metal layers is made of a heavy metal in a metastable state. Spacer layer comprises first material different from the pair of heavy metal layers.

Provided are a magnetic tunneling junction device having a fast operating speed without reducing or with increasing data retention and/or a memory device including the magnetic tunneling junction device. The magnetic tunneling junction device includes a free layer having a first surface and a second surface opposite the first surface; a pinned layer facing the first surface of the free layer; a first oxide layer between the pinned layer and the free layer; and a second oxide layer on the second surface of the free layer. The free layer includes a first free layer adjacent to the first oxide layer and a second free layer adjacent to the second oxide layer. The first free layer includes a magnetic material not doped with a non-magnetic metal, and the second free layer includes a magnetic material doped with the non-magnetic metal.

One or more semiconductor processing tools may deposit one or more tantalum nitride layers on an upper surface of a copper interconnect and within a via. The one or more semiconductor processing tools may deposit an adhesion layer on an upper surface of the one or more tantalum nitride layers and within the via. The one or more semiconductor processing tools may deposit tungsten on an upper surface of the adhesion layer and within the via for via interconnection of the magnetic tunnel junction to the copper interconnect.

The present disclosure provides a method for characterizing magnetic properties of a target layer, including providing a first sample having a first structure, providing a second sample having a target layer over the first structure, obtaining a first magnetic property of the first sample, obtaining a second magnetic property of the second sample, and deriving a third magnetic property of the target layer according to the first magnetic property and the second magnetic property.

A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.