Provided is a semiconductor device including a substrate, a first interconnection structure, and an MTJ device. The first interconnection structure is disposed on the substrate. The MTJ device is reversely bonded to the first interconnection structure. The MTJ device includes a first electrode layer, a second electrode layer and an MTJ stack structure. The first electrode layer is bonded to the first interconnect structure. The second electrode layer is located above the first electrode layer. The MTJ stack structure is located between the first and second electrode layers. The MTJ stack structure includes a first barrier layer, a free layer and a reference layer. The first barrier layer is located between the first and second electrode layers. The free layer is located between the first barrier layer and the first electrode layer. The reference layer is located between the first barrier layer and the second electrode layer.

Provided is a semiconductor device including a substrate, a first interconnection structure, and an MTJ device. The first interconnection structure is disposed on the substrate. The MTJ device is reversely bonded to the first interconnection structure. The MTJ device includes a first electrode layer, a second electrode layer and an MTJ stack structure. The first electrode layer is bonded to the first interconnect structure. The second electrode layer is located above the first electrode layer. The MTJ stack structure is located between the first and second electrode layers. The MTJ stack structure includes a first barrier layer, a free layer and a reference layer. The first barrier layer is located between the first and second electrode layers. The free layer is located between the first barrier layer and the first electrode layer. The reference layer is located between the first barrier layer and the second electrode layer.

A magnetic memory device includes: (i) a reference magnetic pattern and a free magnetic pattern stacked in vertical alignment relative to a surface of a substrate, and (ii) a tunnel barrier pattern extending between the reference magnetic pattern and the free magnetic pattern. The reference magnetic pattern includes: a first pinned pattern, and a second pinned pattern extending between the first pinned pattern and the tunnel barrier pattern, and an exchange coupling pattern, which extends between the first pinned pattern and the second pinned pattern and antiferromagnetically couples the first pinned pattern and the second pinned pattern to each other. The first pinned pattern includes a first magnetic pattern and a second magnetic pattern extending between the first magnetic pattern and the exchange coupling pattern. One of the first magnetic pattern and the second magnetic pattern includes: cobalt, platinum, and a first non-magnetic element comprising at least one of Nb, Cr, Mo, W, Zr, Hf, and Ti, whereas the other one of the first magnetic pattern and the second magnetic pattern includes cobalt.

A magnetic memory device includes: (i) a reference magnetic pattern and a free magnetic pattern stacked in vertical alignment relative to a surface of a substrate, and (ii) a tunnel barrier pattern extending between the reference magnetic pattern and the free magnetic pattern. The reference magnetic pattern includes: a first pinned pattern, and a second pinned pattern extending between the first pinned pattern and the tunnel barrier pattern, and an exchange coupling pattern, which extends between the first pinned pattern and the second pinned pattern and antiferromagnetically couples the first pinned pattern and the second pinned pattern to each other. The first pinned pattern includes a first magnetic pattern and a second magnetic pattern extending between the first magnetic pattern and the exchange coupling pattern. One of the first magnetic pattern and the second magnetic pattern includes: cobalt, platinum, and a first non-magnetic element comprising at least one of Nb, Cr, Mo, W, Zr, Hf, and Ti, whereas the other one of the first magnetic pattern and the second magnetic pattern includes cobalt.

This disclosure provides various methods for improved etching of spin-transfer torque random access memory (STT-RAM) structures. In one example, the method includes (1) ion beam etch of the stack just past the MTJ at near normal incidence, (2) a short clean-up etch at a larger angle in a windowed mode to remove any redeposited material along the sidewall that extends from just below the MTJ to just above the MTJ, (3) deposition of an encapsulant with controlled step coverage to revert to a vertical or slightly re-entrant profile from the tapered profile generated by the etch steps, (4) ion beam etch of the remainder of the stack at near normal incidence while preserving the encapsulation along the sidewall of the MTJ, (5) clean-up etch at a larger angle and windowed mode to remove redeposited materials from the sidewalls, and (6) encapsulation of the etched stack.

A magnetic memory device is provided. The magnetic memory device includes a first magnetic tunnel junction (MTJ) stack, a second MTJ stack, and a spin-orbit torque (SOT) electrode. The second MTJ stack is adjacent to the first MTJ stack. The SOT electrode is connected to the first MTJ stack and the second MTJ stack, wherein the SOT electrode has a first electrode section along a first axis and a second electrode section along a second axis, and the second axis is spaced apart from and parallel to the first axis.

A magnetic memory device is provided. The magnetic memory device includes a first magnetic tunnel junction (MTJ) stack, a second MTJ stack, and a spin-orbit torque (SOT) electrode. The second MTJ stack is adjacent to the first MTJ stack. The SOT electrode is connected to the first MTJ stack and the second MTJ stack, wherein the SOT electrode has a first electrode section along a first axis and a second electrode section along a second axis, and the second axis is spaced apart from and parallel to the first axis.

A semiconductor device including a magnetic tunnel junction (MTJ) stack, where a cross section of a bottom electrode of the MTJ stack comprises a trapezoid profile. A semiconductor device including a lower word line and a first electrode above and connected to the lower word line, where a cross section of an electrode includes a trapezoid profile. A method including forming a bottom electrode, the bottom electrode includes a tapered side surface including a width at an upper surface of the bottom electrode less than a width at a lower surface of the bottom electrode.

A semiconductor device including a magnetic tunnel junction (MTJ) stack, where a cross section of a bottom electrode of the MTJ stack comprises a trapezoid profile. A semiconductor device including a lower word line and a first electrode above and connected to the lower word line, where a cross section of an electrode includes a trapezoid profile. A method including forming a bottom electrode, the bottom electrode includes a tapered side surface including a width at an upper surface of the bottom electrode less than a width at a lower surface of the bottom electrode.

A semiconductor device including a magnetic tunnel junction (MTJ) stack, where a cross section of a bottom electrode of the stack includes a hexagonal profile. A semiconductor device including a lower word line, a magnetic tunnel junction (MTJ) stack, where a cross section of a first electrode of the MTJ stack comprises a hexagonal profile. A method including forming a bottom electrode, the bottom electrode includes a side surface including a width at a middle section of the bottom electrode greater than a width at a lower surface of the bottom electrode, and the width at the middle section of the bottom electrode greater than a width at an upper surface of the bottom electrode.